View source for Intel Core 2 Duo (Merom)

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The Intel 2 Core is the successor of the [[Intel Core Duo (Yonah)]] processor. Unlike the Yonah, the Merom was designed specifically with mobile applications in mind. The Merom introduced various architectural additions such as EM64T, [[SIMD|SSSE3]] and improved the performance by up to 25 percent. The 667 MHz FSB versions are part of the "Napa" platform, while the 800MHz FSB versions are part of the "Santa Rosa" platform. The chip is also part of the hardware from both the Centrino Duo and Centrino Pro brands. The follow-on to Merom is [[Intel_Core_2_Duo_(Penryn)|Penryn]]

=Features=
*Dual Core
*EM64T
*[http://en.wikipedia.org/wiki/Vanderpool#Intel_Virtualization_Technology_.28Intel_VT.29 Intel Virtualization Technology ]
*XD-Bit
*[[SIMD|MMX]], [[SIMD|SSE]], [[SIMD|SSE2]], [[SIMD|SSE3]], [[SIMD|SSSE3]] instruction sets
*667 or 800 MHz FSB
*65 nm fabrication process
*4 MB or 2 MB L2-Cache with dynamic cache sizing
*[[SpeedStep|Enhanced Intel SpeedStep (EIST)]], power states: normal (C0), AutoHALT/MWAIT (C1), Stop Grant (C2), Deep Sleep (C3), [[QuickStart and Deeper Sleep|Deeper Sleep]] (C4)
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=Available Types and ThinkPads featuring them=
==Standard Voltage==
{| border=1 cellspacing=0 cellpadding=2
|- style="background:#ffdead;white-space:nowrap;"
! Name || sSpec || colspan=2 | Frequency (MHz) || L2 Cache || FSB (MHz)|| VT || colspan=2 | core Voltage (V) || colspan=2 | TDP (W) || ThinkPad Models
|- style="background:#ffdead;"
! !! !!max. !! min. !! !! !! !! high !! low !! high freq !! low freq !! 
|-
| T7800 || || 2600 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{T61p}}
|-
| T7700 || || 2400 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}, {{T61p}}
|-
| T7600 || SL9SD || 2333 || 1000 || 4MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{T60}}, {{T60p}}
|-
| T7500 || || 2200 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}, {{X61}}
|-
| T7400 || SL9SE  || 2166 || 1000 || 4MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{T60}}, {{T60p}}, {{Z61t}}
|-
| T7300 || || 2000 || 800   || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}, {{X61}}
|-
| T7200 || SL9SF || 2000 || 1000 || 4MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{R60}}, {{T60}}, {{X60}}, {{Z61m}}, {{Z61t}}
|-
| T7100 || || 1800 || 1000 || 2MB || 800 || yes || ? || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}
|-
| T5870 || || 2000 || ? || 2MB || 800 || yes || ? || ? ||         35 ||        ? || {{R500}}, {{SL300}}, {{SL400}}, {{SL400c}}, {{SL410}}, {{SL500}}, {{SL500c}}, {{SL510}}
|-
| T5750 || || 2000 || ? || 2MB || 667 || no || 1.30 || 1.0375 || 35 || ? || {{R61i}}
|-
| T5670 || || 1800 || 800 || 2MB || 800 || yes || 1.30 || 0.95 || 35 || ? || {{SL300}}, {{SL400}}, {{SL500}}, {{R500}}
|-
| T5600 || || 1833 || 1000 || 2MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{R60}}, {{T60}}, {{X60}}, {{Z61t}}
|-
| T5550 || || 1833 || ? || 2MB || 667 || no || 1.30 || 1.0375 || 35 || ? || {{R61i}}
|-
| T5500 || || 1667 || 1000 || 2MB || 667 || no || 1.30 || 0.95 || 34 || 20 || {{R60}}, {{T60}}, {{X60}}, {{Z61m}}, {{Z61t}}
|-
| T5450 || || 1667 || ? || 2MB || 667 || no || 1.30 || 1.0375 || 35 || ? || {{R61i}}
|-
| T5250 || || 1500 || ? || 2MB || 667 || no || 1.30 || 1.0375 || 35 || ? || {{R61i}}
|}

==Low Voltage==
{| border=1 cellspacing=0 cellpadding=2
|- style="background:#ffdead;white-space:nowrap;"
! Nr. || colspan=2 | Frequency (MHz) || L2 Cache || FSB (MHz)|| VT || colspan=2 | core Voltage (V) || colspan=2 | TDP (W) || ThinkPad Models
|- style="background:#ffdead;"
! !!max. !! min. !! !! !! !! high !! low !! high freq !! low freq !! 
|-
| L7400 || 1500 || 1000 || 4MB || 667 || yes || 1.2 || 0.85 - 0.9 || 17 || ? || {{X60s}}, {{X60_Tablet}}
|-
| L7500 || 1600 || 800 || 4MB || 800 || yes || 1.1 || 0.85 - 0.9 || 17 || ? || {{X61s}}, {{X61_Tablet}}
|-
| L7700 || 1800 || 800 || 4MB || 800 || yes || 1.1 || 0.85 - 0.9 || 17 || ? || {{X61s}}, {{X61_Tablet}}
|-
| SL7100 || 1200 || 800 || 4MB || 800 || yes || 1.1 || 0.85 - 0.9 || 12 || ? || {{X300}}
|}

As you can see, the Low-Voltage CPU's work at the same Voltage as the normal CPUs when running in SLFM. With a simple tool (RMClock) you can use those lower voltages at every clock.
Intel gave other voltage-regions for the CPUs:

''the standard processor that works on a core voltage between 1.075V and 1.175V, the low voltage processors that work between 0.975V and 1.062V and finally the ultra low voltage processors that work between 0.80V and 0.975V.''

Intel doesn't think of the SLFM. With SLFM and a little bit luck, you're T-CPU can be thriftier than a LV-CPU but has more power.
With RMClock every T-CPU is thriftier than a LV-CPU, because you have the same voltage but a higher max-clock, so the sleep-states can be longer.

=Thermal Specifications=
The maximum temperature for safe operation is 100°C.

The catastrophic thermal protection temperature is 125°C.

Idle temperature is typically around 30-50°C.

Temperature at full utilisation is around 60-70°C.

These latter two values will of course depend largely on cooling systems and available airflow.

=Compiler optimisation flags=
==GCC==
In addition to the architecture independent <code>-O[0123s]</code> option hierarchy, architecture dependent optimisations are controlled by the <code>-march=<cpu-type></code> and <code>-mtune=<cpu-type></code> options. The <cpu-type> argument (not surprisingly) describes the type of cpu for which to optimise the compiled code. The <code>-mtune</code> option will generate code that is optimised for the given cpu type which will nevertheless run on cpu types other than the optimisation target. On the other hand, <code>-march</code> will attempt to optimise more aggressively at the expense of reducing portability to other cpu types. Optimisations implied by <code>-mtune</code> are a subset of <code>-march</code> optimisations, and thus it is only necessary to specify <code>-march</code> if the the maximum level of optimisation is desired.

With version of gcc before 4.3, 32-bit code should be compiled with the "prescott" as the cpu-type argument to <code>-march</code> or <code>-mtune</code> whereas 64-bit code should use the "nocona" argument. Gcc 4.3 however introduces "core2" as a valid argument to the <code>-mtune</code> and <code>-march</code> options which should be used. Alternatively, as of gcc 4.2, the "native" argument is supported. This will automatically determine the cpu-type on which compilation is taking place and apply optimisations specific to that cpu.

==Intel==
For the [http://www.spec.org/cpu2006/ SPEC CPU 2006 benchmarks], Intel used the shorthand <code>-fast</code>, which translates into <code>-O3 -ipo -static -no-prec-div -xP</code>. However, the compiler also provides the flag <code>-xT</code>, which activates the optimization for Core 2 Duo and SSSE3 (instead of SSE3 only with <code>-xP</code>).

=Microcode=
Much like software products, bugs, errata or ways to improve upon operation are often found in CPU's after they have reached the market. In some cases, the necessary changes can be applied by the end user without any change to the underlying hardware in the form of microcode updates downloadable from the manufacturer. Intel offers these microcode updates for download on their [http://downloadcenter.intel.com/Detail_Desc.aspx?ProductID=2676&DwnldID=14303&lang=eng website]. 

Provided the availability of the <tt>microcode</tt> and <tt>firmware</tt> kernel modules (which are enabled in the stock kernels of most distributions) and a suitable user space tool such as [http://urbanmyth.org/microcode/ microcode_ctl], one can install the updated microcode into their processors at runtime. The microcode update is volatile however, meaning that it disappears upon reboot. While this reduces the risk of applying such an update to essentially 0, it does mean that it must be applied on each boot.
==Debian==
You can install the microcode.ctl package which will take care of everything (including downloading the microcode itself) for you. Just run
{{cmdroot|aptitude install microcode.ctl}}. This package includes an init script which will run at boot to load the microcode into the processor. This script also contains a line which will remove the <tt>microcode</tt> kernel module once the operation is complete and it is no longer needed, however it  is strangely commented out by default. If you want to keep your loaded modules (used memory) to a minimum, you can edit {{path|/etc/init.d/microcode.ctl}} and uncomment the line
<pre>
[ -x /sbin/modprobe ] && /sbin/modprobe -r microcode > /dev/null 2> /dev/null
</pre>
==Gentoo==
The <tt>microcode-ctl</tt> utility can be installed as follows: {{cmdroot|emerge microcode-ctl}}. This will create an init script <tt>/etc/init.d/microcode_ctl</tt>, but will not automatically set it to run on startup; to do so, run {{cmdroot|rc-update add microcode_ctl boot}}. Also, this will install an old copy of the microcode to <tt>/etc/microcode.dat</tt>; to update it, download a new copy from the link above and replace this file.

=Note on Hyper-Threading=
Note that as opposed to Pentium 4/NetBurst, current Core 2 do not support hyper-threading, and therefore there is usually no option in the BIOS to activate it. Refer to Intel's [http://www.intel.com/products/ht/hyperthreading_more.htm Hyper-Threading Technology] for a list of hyper-threading capable CPU.

=See also=
*[[Intel Core Solo (Yonah)]]
*[[Intel Core Duo (Yonah)]]
*[[Intel Core 2 Duo (Penryn)]]

== External Links ==
*[http://www.intel.com/products/processor_number/chart/core2duo.htm  Intel - Processor Numbers and Features]
*[http://en.wikipedia.org/wiki/List_of_Intel_Core_2_microprocessors#Mobile_processors Wikipedia - Intel Core 2 mobile microprocessors]

[[Category:Components]]