Intel Core Solo (Yonah) - Revision history

Bugmenot2: changed category

2021-01-22T14:50:58Z

changed category

2008-03-01T17:20:37Z

CPU U1400 added

2008-02-29T01:56:55Z

2007-08-20T00:56:00Z

‎Features: add link to deeper sleep

2006-10-15T21:16:03Z

‎Intel Core Solo (Yonah)

2006-10-11T16:45:53Z

‎GCC Optimization Flags

2006-02-28T12:11:58Z

‎GCC Optimization Flags

2006-02-27T22:57:27Z

2006-02-12T02:33:11Z

‎Available Types and ThinkPads featuring them

2006-01-15T12:58:46Z

‎Available Types and ThinkPads featuring them

← Older revision		Revision as of 14:50, 22 January 2021
Line 48:		Line 48:
	[[Intel_Core_Duo_(Yonah)\|Intel Core Duo (Yonah)]]		[[Intel_Core_Duo_(Yonah)\|Intel Core Duo (Yonah)]]

−	[[Category:~~Components~~]]	+	[[Category:CPUs]]

@@ Line 7: / Line 7: @@
 ==Features==
-*1.66 GHz clock speed
+*1.2 - 1.66 GHz clock speed
-*667 MHz FSB
+*667 MHz FSB; 533 MHz for ULV CPU
-*27 watt thermal design power consumption
+*5.5 (ultra low voltage) or 27 (normal voltage) watt thermal design power consumption
 *151 Million Transistors
 *65 nm process
@@ Line 27: / Line 27: @@
 ! colspan="10" | Intel Core Solo
 |-
-| T1300 || 1666 || 1000 || 667 || yes || 1.2 || ... || 27 || 13.1 || {{X60}}, {{T60}}
+| T1300 || 1666 || 1000 || 667 || yes || 1.2 || ... || 27   || 13.1 || {{X60}}, {{T60}}
 |}

@@ Line 3: / Line 3: @@
 |style="vertical-align:top" |
 <div style="margin: 0; margin-right:10px; border: 1px solid #dfdfdf; padding: 0em 1em 1em 1em; background-color:#F8F8FF; align:right;">
-===Intel Core Solo (Yonah)===
 The Intel Core Solo is the successor to the [[Intel_Pentium_M_(Dothan)|Pentium M processor]]. The chip uses Intel's 65 nm process (compared to 90 nm for the Pentium M). The Intel Core processors feature a 667 MHz FSB and are shipped as part of the Napa Centrino platform.
-===Features===
+==Features==
 *1.66 GHz clock speed
 *667 MHz FSB

@@ Line 13: / Line 13: @@
 *65 nm process
 *2 MB L2-Cache
-*[[SpeedStep|Enhanced Intel SpeedStep (EIST)]], power states: normal (C0), AutoHALT/MWAIT (C1), Stop Grant (C2), Deep Sleep (C3), Deeper Sleep (C4)
+*[[SpeedStep|Enhanced Intel SpeedStep (EIST)]], power states: normal (C0), AutoHALT/MWAIT (C1), Stop Grant (C2), Deep Sleep (C3), [[QuickStart and Deeper Sleep|Deeper Sleep]] (C4)
 *[[SIMD|MMX]], [[SIMD|SSE]], [[SIMD|SSE2]], [[SIMD|SSE3]] instruction sets, XD-Bit
 </div>

@@ Line 4: / Line 4: @@
 <div style="margin: 0; margin-right:10px; border: 1px solid #dfdfdf; padding: 0em 1em 1em 1em; background-color:#F8F8FF; align:right;">
 ===Intel Core Solo (Yonah)===
-The Intel Core Solo is the successor of the [[Intel_Pentium_M_(Dothan)|Pentium M processor]]. The structures were shrinked again to 65 nm. The Intel Core processors feature a 667 MHz FSB and accompany the Napa Centrino platform.
+The Intel Core Solo is the successor to the [[Intel_Pentium_M_(Dothan)|Pentium M processor]]. The chip uses Intel's 65 nm process (compared to 90 nm for the Pentium M). The Intel Core processors feature a 667 MHz FSB and are shipped as part of the Napa Centrino platform.
 ===Features===

@@ Line 35: / Line 35: @@
 ==GCC Optimization Flags==
 Safe, recommended optimizations for GCC 3.4.x and later:
-  -pipe -O2 -march=pentium-m -msse3 -fomit-frame-pointer
+  -pipe -O2 -march=prescott -fomit-frame-pointer
 Possibly unsafe optimizations for GCC 3.3.x and later:

← Older revision		Revision as of 12:11, 28 February 2006
Line 34:		Line 34:

	==GCC Optimization Flags==		==GCC Optimization Flags==
		+	Safe, recommended optimizations for GCC 3.4.x and later:
		+	-pipe -O2 -march=pentium-m -msse3 -fomit-frame-pointer
		+
		+	Possibly unsafe optimizations for GCC 3.3.x and later:
		+	-mfpmath=sse
		+
		+	Optimizations likely to break binary-only compatibility:
		+	-ffast-math

	==See also==		==See also==

@@ Line 25: / Line 25: @@
 ! !!max. !! min. !! !! !! high !! low !! high !! low !!
 |- style="background:#efefef;"
-! colspan=10 colspan="3" | Intel Core Solo
+! colspan="10" | Intel Core Solo
 |-
 | T1300 || 1666 || 1000 || 667 || yes || 1.2 || ... || 27 || 13.1 || {{X60}}