Intel Core 2 Duo (Merom) - Revision history

ThinkGNU: Grammar. It's hard to tell what the SLFM section is claiming, but from what I can tell you can run a T series CPU at a similar voltage as a Low voltage CPU, but with a higher clock. Fixed dead link.

2025-04-11T01:00:23Z

Grammar. It's hard to tell what the SLFM section is claiming, but from what I can tell you can run a T series CPU at a similar voltage as a Low voltage CPU, but with a higher clock. Fixed dead link.

Bugmenot2: changed category

2021-01-22T14:48:52Z

changed category

Dsrg at 08:26, 13 December 2016

2016-12-13T08:26:16Z

Vrossum: /* Standard Voltage */

2011-01-29T21:58:30Z

‎Standard Voltage

Tonko: /* Standard Voltage */

2010-03-02T16:20:43Z

‎Standard Voltage

Tonko: /* Standard Voltage */

2010-02-05T15:44:26Z

‎Standard Voltage

Tonko: /* Standard Voltage */

2010-02-05T15:23:18Z

‎Standard Voltage

Tonko: /* Standard Voltage */

2010-02-05T14:18:48Z

‎Standard Voltage

Tonko: /* Standard Voltage */

2010-02-05T14:08:08Z

‎Standard Voltage

Tonko: /* Standard Voltage */

2010-02-05T13:19:35Z

‎Standard Voltage

@@ Line 76: / Line 76: @@
 |}
-As you can see, the Low-Voltage CPU's work at the same Voltage as the normal CPUs when running in SLFM. With a simple tool (RMClock) you can use those lower voltages at every clock.
+As you can see, the Low-Voltage CPU's work at the same Voltage as the normal CPUs when running in SLFM (Super Low Frequency Mode). With a simple tool (RMClock) you can use those lower voltages at every clock.
 Intel gave other voltage-regions for the CPUs:
 ''the standard processor that works on a core voltage between 1.075V and 1.175V, the low voltage processors that work between 0.975V and 1.062V and finally the ultra low voltage processors that work between 0.80V and 0.975V.''
-Intel doesn't think of the SLFM. With SLFM and a little bit luck, you're T-CPU can be thriftier than a LV-CPU but has more power.
+Intel doesn't think of the SLFM. With SLFM and a little bit of luck, your T-CPU can be thriftier than a LV-CPU with only a little more power.
 With RMClock every T-CPU is thriftier than a LV-CPU, because you have the same voltage but a higher max-clock, so the sleep-states can be longer.
@@ Line 99: / Line 99: @@
 In addition to the architecture independent <code>-O[0123s]</code> option hierarchy, architecture dependent optimisations are controlled by the <code>-march=<cpu-type></code> and <code>-mtune=<cpu-type></code> options. The <cpu-type> argument (not surprisingly) describes the type of cpu for which to optimise the compiled code. The <code>-mtune</code> option will generate code that is optimised for the given cpu type which will nevertheless run on cpu types other than the optimisation target. On the other hand, <code>-march</code> will attempt to optimise more aggressively at the expense of reducing portability to other cpu types. Optimisations implied by <code>-mtune</code> are a subset of <code>-march</code> optimisations, and thus it is only necessary to specify <code>-march</code> if the the maximum level of optimisation is desired.
-With version of gcc before 4.3, 32-bit code should be compiled with the "prescott" as the cpu-type argument to <code>-march</code> or <code>-mtune</code> whereas 64-bit code should use the "nocona" argument. Gcc 4.3 however introduces "core2" as a valid argument to the <code>-mtune</code> and <code>-march</code> options which should be used. Alternatively, as of gcc 4.2, the "native" argument is supported. This will automatically determine the cpu-type on which compilation is taking place and apply optimisations specific to that cpu.
+With version of gcc before 4.3, 32-bit code should be compiled with the "prescott" as the cpu-type argument to <code>-march</code> or <code>-mtune</code> whereas 64-bit code should use the "nocona" argument. Gcc 4.3 however introduces "core2" as a valid argument to the <code>-mtune</code> and <code>-march</code> options which should be used. Alternatively, as of gcc 4.2, the "native" argument is supported. This will automatically determine the cpu-type while compilation is taking place and apply optimisations specific to that cpu.
 ==Intel==
@@ Line 118: / Line 118: @@
 =Note on Hyper-Threading=
-Note that as opposed to Pentium 4/NetBurst, current Core 2 do not support hyper-threading, and therefore there is usually no option in the BIOS to activate it. Refer to Intel's [http://www.intel.com/products/ht/hyperthreading_more.htm Hyper-Threading Technology] for a list of hyper-threading capable CPU.
+Note that as opposed to Pentium 4/NetBurst, Core 2 Duo's do not support hyper-threading, and therefore there is no option in the BIOS to activate it. Refer to Intel's [https://web.archive.org/web/20091002193803if_/http://www.intel.com:80/products/ht/Hyperthreading_more.htm Hyper-Threading Technology] for a list of hyper-threading capable CPUs.
 =See also=

← Older revision		Revision as of 14:48, 22 January 2021
Line 129:		Line 129:
	*[http://en.wikipedia.org/wiki/List_of_Intel_Core_2_microprocessors#Mobile_processors Wikipedia - Intel Core 2 mobile microprocessors]		*[http://en.wikipedia.org/wiki/List_of_Intel_Core_2_microprocessors#Mobile_processors Wikipedia - Intel Core 2 mobile microprocessors]

−	[[Category:~~Components~~]]	+	[[Category:CPUs]]

@@ Line 33: / Line 33: @@
 | T7600 || SL9SD || 2333 || 1000 || 4MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{T60}}, {{T60p}}
 |-
-| T7500 || || 2200 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}, {{X61}}
+| T7500 || || 2200 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}, {{T61p}}, {{X61}}
 |-
 | T7400 || SL9SE  || 2166 || 1000 || 4MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{T60}}, {{T60p}}, {{Z61t}}

@@ Line 41: / Line 41: @@
 | T7200 || SL9SF || 2000 || 1000 || 4MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{R60}}, {{T60}}, {{X60}}, {{Z61m}}, {{Z61t}}
 |-
-| T7100 || || 1800 || 1000 || 2MB || 800 || yes || ? || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}
+| T7100 || || 1800 || 1000 || 2MB || 800 || yes || ? || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}, {{X61}}
 |-
 | T5870 || || 2000 || ? || 2MB || 800 || yes || ? || ? ||         35 ||        ? || {{R500}}, {{SL300}}, {{SL400}}, {{SL400c}}, {{SL410}}, {{SL500}}, {{SL500c}}, {{SL510}}

@@ Line 44: / Line 44: @@
 |-
 | T5870 || || 2000 || ? || 2MB || 800 || yes || ? || ? ||         35 ||        ? || {{R500}}, {{SL300}}, {{SL400}}, {{SL400c}}, {{SL410}}, {{SL500}}, {{SL500c}}, {{SL510}}
 |-
 | T5670 || || 1800 || 800 || 2MB || 800 || yes || 1.30 || 0.95 || 35 || ? || {{SL300}}, {{SL400}}, {{SL500}}, {{R500}}
@@ Line 49: / Line 51: @@
 | T5600 || || 1833 || 1000 || 2MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{R60}}, {{T60}}, {{X60}}, {{Z61t}}
 |-
-| T5500 || || 1666 || 1000 || 2MB || 667 || no || 1.30 || 0.95 || 34 || 20 || {{R60}}, {{T60}}, {{X60}}, {{Z61m}}, {{Z61t}}
+| T5550 || || 1833 || ? || 2MB || 667 || no || 1.30 || 1.0375 || 35 || ? || {{R61i}}
 |}

@@ Line 43: / Line 43: @@
 | T7100 || || 1800 || 1000 || 2MB || 800 || yes || ? || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}
 |-
-| T5870 || || 2000 || ? || 2MB || 800 || yes || ? || ? ||         35 ||        ? || {{R500}}, {{SL300}}, {{SL400}}, {{SL400c}}, {{SL500}}
+| T5870 || || 2000 || ? || 2MB || 800 || yes || ? || ? ||         35 ||        ? || {{R500}}, {{SL300}}, {{SL400}}, {{SL400c}}, {{SL500}}, {{SL500c}}
 |-
 | T5670 || || 1800 || 800 || 2MB || 800 || yes || 1.30 || 0.95 || 35 || ? || {{SL300}}, {{SL400}}, {{SL500}}, {{R500}}