ThinkWiki - User contributions [en]

MiniPCI Express slot

2011-05-20T03:17:58Z

Notpeter: link to Thinkpad BIOS which enables 3rd party mini PCIe devices

{| width="100%"
<div style="margin: 0; margin-right:10px; border: 1px solid #dfdfdf; padding: 0em 1em 1em 1em; background-color:#F8F8FF; align:right;">
A MiniPCI Express slot is a version of the PCI-Express x1 slot for Notebooks.

* [http://en.wikipedia.org/wiki/PCI_Express#PCI_Express_Mini_Card Wikipedia article on Mini PCI Express]

{{NOTE|There are two physical form factors, a standard 30×50.95 mm, and a half-height 30×26.8 mm. Some ThinkPads only support the later}}
</div>
|}
__NOTOC__

=== MiniPCI Express Adapters ===
'''WLAN'''
* [[Intel PRO/Wireless 3945ABG Mini-PCI Express Adapter]]
* [[Intel PRO/Wireless 4965AGN Mini-PCI Express Adapter]]
* [[Intel Wifi Link 5100 (AGN)]]
* [[Intel Wifi Link 5300 (AGN)]]
* [[Intel WiMAX/WiFi Link 5150]]
* [[Intel WiMAX/WiFi Link 5350]]
* [[Intel Centrino Wireless-N 1000]]
* [[Intel Centrino Advanced-N 6200]]
* [[Intel Centrino Advanced-N + WiMAX 6250]]
* [[Intel Centrino Ultimate-N 6300]]
* [[ThinkPad 11a/b/g/n Wireless LAN Mini Express Adapter]]
* [[ThinkPad 11a/b/g Wireless LAN Mini Express Adapter]]
* [[ThinkPad 11b/g/n Wireless LAN Mini-PCI Express Adapter II]]
'''WWAN'''
* [[Sierra Wireless MC5720]] - EV-DO WWAN
* [[Sierra Wireless MC5725]] - EV-DO WWAN
* [[Sierra Wireless HSDPA WWAN]]
* [[Ericsson F3507g Mobile Broadband Module]]
* [[Qualcomm Gobi 2000]]
'''Other'''
* [[Intel® Turbo Memory hard drive cache]]
* [[Wireless USB (UWB)]]

=== (In)Compatibility ===
Though the slot is MiniPCIe in form factor, it has been crippled to only accept devices with PCI-ID's contained in a BIOS whitelist consisting of the above list of devices (likely not exhaustive and varying depending on the particular system) with the additional requirement that they '''must carry the Lenovo brand name and consequently cost twice as much'''. If an unauthorized card is plugged in it gives a <tt>1802</tt> error on initial boot up before it even touches the operating system. (see [[Problem with unauthorized MiniPCI network card]], [http://forum.notebookreview.com/showthread.php?t=69445 1802 with MiniPCIe on t60],[http://forums.lenovo.com/lnv/board/message?board.id=T_Series_Thinkpads&message.id=274 same]). The workarounds on the first link concerning MiniPCI devices may or may not be directly applicable to the MiniPCIe slot. Anyone who has added non-Lenovo components to this slot either successfully or unsuccessfully is encouraged to provide any relevant details here.

=== Hacked BIOS with white list removed ===
Non-official patched versions of BIOS files are available for X300, X61, X61s, T61, T61p, R61, R61e which remove whitelist restrictions allowing non-lenovo PCI-e devices.. (see forum post: [http://forum.notebookreview.com/lenovo-ibm/459591-t61-x61-sata-ii-1-5-gb-s-cap-willing-pay-solution-8.html#post6501443 Ultimate R61/T61/X61/X300 BIOS (inc SATA-II)]

=== Linux support ===
MiniPCI Express adapters are handled by the Linux PCI subsystem.

=== Models featuring this Technology ===
* ThinkPad {{Edge 11"}}, {{Edge 13"}}, {{Edge 14"}}, {{Edge 15"}}
* ThinkPad {{L Series}}
* ThinkPad {{R60}}, {{R60e}}, {{R61}}, {{R61e}}, {{R61i}}, {{R400}}, {{R500}}
* ThinkPad {{SL300}}, {{SL400}}, {{SL400c}}, {{SL410}}, {{SL500}}, {{SL500c}}, {{SL510}}
* ThinkPad {{T60}}, {{T60p}}, {{T61}}, {{T61p}}, {{T400}}, {{T400s}}, {{T410}}, {{T410i}}, {{T410s}}, {{T410si}}, {{T500}}, {{T510}}, {{T510i}}
* ThinkPad {{W Series}}
* ThinkPad {{X60}}, {{X60s}}, {{X60 Tablet}}, {{X61}}, {{X61s}}, {{X61 Tablet}}, {{X100e}}, {{X200}}, {{X200s}}, {{X200 Tablet}}, {{X201}}, {{X201i}}, {{X201s}}, {{X201 Tablet}}, {{X220}}, {{X300}}, {{X301}}
* ThinkPad {{Z Series}}

[[Category:Components]]

=== External sources ===
* Lenovo [ftp://ftp.software.ibm.com/pc/pccbbs/mobiles/accessories_guide_us_can_dec2007.pdf accessories guide].

Intel Core 2 Duo (Merom)

2008-07-15T15:19:59Z

Notpeter: /* Features */

{| width="100%"
|style="vertical-align:top;padding-right:20px;width:10px;white-space:nowrap;" | __TOC__
|style="vertical-align:top" |
<div style="margin: 0; margin-right:10px; border: 1px solid #dfdfdf; padding: 0em 1em 1em 1em; background-color:#F8F8FF; align:right;">

The Intel 2 Core is the successor of the [[Intel Core Duo (Yonah)]] processor. Unlike the Yonah, the Merom was designed specifically with mobile applications in mind. The Merom introduced various architectural additions such as EM64T, [[SIMD|SSSE3]] and improved the performance by up to 25 percent. The 667 MHz FSB versions are part of the "Napa" platform, while the 800MHz FSB versions are part of the "Santa Rosa" platform. The chip is also part of the hardware from both the Centrino Duo and Centrino Pro brands.

=Features=
*Dual Core
*EM64T
*[http://en.wikipedia.org/wiki/Vanderpool#Intel_Virtualization_Technology_.28Intel_VT.29 Intel Virtualization Technology ]
*XD-Bit
*[[SIMD|MMX]], [[SIMD|SSE]], [[SIMD|SSE2]], [[SIMD|SSE3]], [[SIMD|SSSE3]] instruction sets
*667 or 800 MHz FSB
*65 nm fabrication process
*4 MB or 2 MB L2-Cache with dynamic cache sizing
*[[SpeedStep|Enhanced Intel SpeedStep (EIST)]], power states: normal (C0), AutoHALT/MWAIT (C1), Stop Grant (C2), Deep Sleep (C3), [[QuickStart and Deeper Sleep|Deeper Sleep]] (C4)
</div>
|}

=Available Types and ThinkPads featuring them=
==Standard Voltage==
{| border=1 cellspacing=0 cellpadding=2
|- style="background:#ffdead;white-space:nowrap;"
! Nr. || colspan=2 | Frequency (MHz) || L2 Cache || FSB (MHz)|| VT || colspan=2 | core Voltage (V) || colspan=2 | TDP (W) || ThinkPad Models
|- style="background:#ffdead;"
! !!max. !! min. !! !! !! !! high !! low !! high freq !! low freq !!
|-
| T8300 || 2400 || 800 || 3MB || 800 || yes || 1.25 || 1 ? || ? || ? || {{X61}}
|-
| T7800 || 2600 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{T61p}}
|-
| T7700 || 2400 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}, {{T61p}}
|-
| T7600 || 2333 || 1000 || 4MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{T60}}, {{T60p}}
|-
| T7500 || 2200 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}, {{X61}}
|-
| T7400 || 2166 || 1000 || 4MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{T60}}, {{T60p}}, {{Z61t}}
|-
| T7300 || 2000 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}, {{X61}}
|-
| T7200 || 2000 || 1000 || 4MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{R60}}, {{T60}}, {{X60}}, {{Z61m}}, {{Z61t}}
|-
| T7100 || 1800 || 1000 || 2MB || 800 || yes || ? || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}
|-
| T5600 || 1833 || 1000 || 2MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{R60}}, {{T60}}, {{X60}}, {{Z61t}}
|-
| T5500 || 1666 || 1000 || 2MB || 667 || no || 1.30 || 0.95 || 34 || 20 || {{R60}}, {{T60}}, {{X60}}, {{Z61m}}, {{Z61t}}
|}

==Low Voltage==
{| border=1 cellspacing=0 cellpadding=2
|- style="background:#ffdead;white-space:nowrap;"
! Nr. || colspan=2 | Frequency (MHz) || L2 Cache || FSB (MHz)|| VT || colspan=2 | core Voltage (V) || colspan=2 | TDP (W) || ThinkPad Models
|- style="background:#ffdead;"
! !!max. !! min. !! !! !! !! high !! low !! high freq !! low freq !!
|-
| L7400 || 1500 || 1000 || 4MB || 667 || yes || 1.2 || 0.85 - 0.9 || 17 || ? || {{X60s}}, {{X60_Tablet}}
|-
| L7500 || 1600 || 800 || 4MB || 800 || yes || 1.1 || 0.85 - 0.9 || 17 || ? || {{X61s}}, {{X61_Tablet}}
|-
| L7700 || 1800 || 800 || 4MB || 800 || yes || 1.1 || 0.85 - 0.9 || 17 || ? || {{X61s}}, {{X61_Tablet}}
|-
| SL7100 || 1200 || 800 || 4MB || 800 || yes || 1.1 || 0.85 - 0.9 || 12 || ? || {{X300}}
|}

As you can see, the Low-Voltage CPU's work at the same Voltage as the normal CPUs when running in SLFM. With a simple tool (RMClock) you can use those lower voltages at every clock.
Intel gave other voltage-regions for the CPUs:

''the standard processor that works on a core voltage between 1.075V and 1.175V, the low voltage processors that work between 0.975V and 1.062V and finally the ultra low voltage processors that work between 0.80V and 0.975V.''

Intel doesn't think of the SLFM. With SLFM and a little bit luck, you're T-CPU can be thriftier than a LV-CPU but has more power.
With RMClock every T-CPU is thriftier than a LV-CPU, because you have the same voltage but a higher max-clock, so the sleep-states can be longer.

=Thermal Specifications=
The maximum temperature for safe operation is 100°C.

The catastrophic thermal protection temperature is 125°C.

Idle temperature is typically around 30-50°C.

Temperature at full utilisation is around 60-70°C.

These latter two values will of course depend largely on cooling systems and available airflow.

=Compiler optimisation flags=
==GCC==
In addition to the architecture independent <code>-O[0123s]</code> option hierarchy, architecture dependent optimisations are controlled by the <code>-march=<cpu-type></code> and <code>-mtune=<cpu-type></code> options. The <cpu-type> argument (not surprisingly) describes the type of cpu for which to optimise the compiled code. The <code>-mtune</code> option will generate code that is optimised for the given cpu type which will nevertheless run on cpu types other than the optimisation target. On the other hand, <code>-march</code> will attempt to optimise more aggressively at the expense of reducing portability to other cpu types. Optimisations implied by <code>-mtune</code> are a subset of <code>-march</code> optimisations, and thus it is only necessary to specify <code>-march</code> if the the maximum level of optimisation is desired.

With version of gcc before 4.3, 32-bit code should be compiled with the "prescott" as the cpu-type argument to <code>-march</code> or <code>-mtune</code> whereas 64-bit code should use the "nocona" argument. Gcc 4.3 however introduces "core2" as a valid argument to the <code>-mtune</code> and <code>-march</code> options which should be used. Alternatively, as of gcc 4.2, the "native" argument is supported. This will automatically determine the cpu-type on which compilation is taking place and apply optimisations specific to that cpu.

==Intel==
For the [http://www.spec.org/cpu2006/ SPEC CPU 2006 benchmarks], Intel used the shorthand <code>-fast</code>, which translates into <code>-O3 -ipo -static -no-prec-div -xP</code>. However, the compiler also provides the flag <code>-xT</code>, which activates the optimization for Core 2 Duo and SSSE3 (instead of SSE3 only with <code>-xP</code>).

=Microcode=
Much like software products, bugs, errata or ways to improve upon operation are often found in CPU's after they have reached the market. In some cases, the necessary changes can be applied by the end user without any change to the underlying hardware in the form of microcode updates downloadable from the manufacturer. Intel offers these microcode updates for download on their [http://downloadcenter.intel.com/Detail_Desc.aspx?ProductID=2676&DwnldID=14303&lang=eng website].

Provided the availability of the <tt>microcode</tt> and <tt>firmware</tt> kernel modules (which are enabled in the stock kernels of most distributions) and a suitable user space tool such as [http://urbanmyth.org/microcode/ microcode_ctl], one can install the updated microcode into their processors at runtime. The microcode update is volatile however, meaning that it disappears upon reboot. While this reduces the risk of applying such an update to essentially 0, it does mean that it must be applied on each boot.
==Debian==
You can install the microcode.ctl package which will take care of everything (including downloading the microcode itself) for you. Just run
{{cmdroot|aptitude install microcode.ctl}}. This package includes an init script which will run at boot to load the microcode into the processor. This script also contains a line which will remove the <tt>microcode</tt> kernel module once the operation is complete and it is no longer needed, however it is strangely commented out by default. If you want to keep your loaded modules (used memory) to a minimum, you can edit {{path|/etc/init.d/microcode.ctl}} and uncomment the line
<pre>
[ -x /sbin/modprobe ] && /sbin/modprobe -r microcode > /dev/null 2> /dev/null
</pre>
==Gentoo==
The <tt>microcode-ctl</tt> utility can be installed as follows: {{cmdroot|emerge microcode-ctl}}. This will create an init script <tt>/etc/init.d/microcode_ctl</tt>, but will not automatically set it to run on startup; to do so, run {{cmdroot|rc-update add microcode_ctl boot}}. Also, this will install an old copy of the microcode to <tt>/etc/microcode.dat</tt>; to update it, download a new copy from the link above and replace this file.

=Note on Hyper-Threading=
Note that as opposed to Pentium 4/NetBurst, current Core 2 do not support hyper-threading, and therefore there is usually no option in the BIOS to activate it. Refer to Intel's [http://www.intel.com/products/ht/hyperthreading_more.htm Hyper-Threading Technology] for a list of hyper-threading capable CPU.

=See also=
[[Intel_Core_Solo_(Yonah)|Intel Core Solo (Yonah)]]

[[Intel Core Duo (Yonah)]]

== External Links ==
*[http://www.intel.com/products/processor_number/chart/core2duo.htm Intel - Processor Numbers and Features]
*[http://en.wikipedia.org/wiki/List_of_Intel_Core_2_microprocessors#Mobile_processors Wikipedia - Intel Core 2 mobile microprocessors]

[[Category:Components]]

Intel Core 2 Duo (Merom)

2008-07-15T15:18:18Z

Notpeter: /* Features */

{| width="100%"
|style="vertical-align:top;padding-right:20px;width:10px;white-space:nowrap;" | __TOC__
|style="vertical-align:top" |
<div style="margin: 0; margin-right:10px; border: 1px solid #dfdfdf; padding: 0em 1em 1em 1em; background-color:#F8F8FF; align:right;">

The Intel 2 Core is the successor of the [[Intel Core Duo (Yonah)]] processor. Unlike the Yonah, the Merom was designed specifically with mobile applications in mind. The Merom introduced various architectural additions such as EM64T, [[SIMD|SSSE3]] and improved the performance by up to 25 percent. The 667 MHz FSB versions are part of the "Napa" platform, while the 800MHz FSB versions are part of the "Santa Rosa" platform. The chip is also part of the hardware from both the Centrino Duo and Centrino Pro brands.

=Features=
*Dual Core
*EM64T
*[Intel Virtualization Technoloy | http://en.wikipedia.org/wiki/Vanderpool#Intel_Virtualization_Technology_.28Intel_VT.29]
*XD-Bit
*[[SIMD|MMX]], [[SIMD|SSE]], [[SIMD|SSE2]], [[SIMD|SSE3]], [[SIMD|SSSE3]] instruction sets
*667 or 800 MHz FSB
*65 nm fabrication process
*4 MB or 2 MB L2-Cache with dynamic cache sizing
*[[SpeedStep|Enhanced Intel SpeedStep (EIST)]], power states: normal (C0), AutoHALT/MWAIT (C1), Stop Grant (C2), Deep Sleep (C3), [[QuickStart and Deeper Sleep|Deeper Sleep]] (C4)
</div>
|}

=Available Types and ThinkPads featuring them=
==Standard Voltage==
{| border=1 cellspacing=0 cellpadding=2
|- style="background:#ffdead;white-space:nowrap;"
! Nr. || colspan=2 | Frequency (MHz) || L2 Cache || FSB (MHz)|| VT || colspan=2 | core Voltage (V) || colspan=2 | TDP (W) || ThinkPad Models
|- style="background:#ffdead;"
! !!max. !! min. !! !! !! !! high !! low !! high freq !! low freq !!
|-
| T8300 || 2400 || 800 || 3MB || 800 || yes || 1.25 || 1 ? || ? || ? || {{X61}}
|-
| T7800 || 2600 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{T61p}}
|-
| T7700 || 2400 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}, {{T61p}}
|-
| T7600 || 2333 || 1000 || 4MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{T60}}, {{T60p}}
|-
| T7500 || 2200 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}, {{X61}}
|-
| T7400 || 2166 || 1000 || 4MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{T60}}, {{T60p}}, {{Z61t}}
|-
| T7300 || 2000 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}, {{X61}}
|-
| T7200 || 2000 || 1000 || 4MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{R60}}, {{T60}}, {{X60}}, {{Z61m}}, {{Z61t}}
|-
| T7100 || 1800 || 1000 || 2MB || 800 || yes || ? || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}
|-
| T5600 || 1833 || 1000 || 2MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{R60}}, {{T60}}, {{X60}}, {{Z61t}}
|-
| T5500 || 1666 || 1000 || 2MB || 667 || no || 1.30 || 0.95 || 34 || 20 || {{R60}}, {{T60}}, {{X60}}, {{Z61m}}, {{Z61t}}
|}

==Low Voltage==
{| border=1 cellspacing=0 cellpadding=2
|- style="background:#ffdead;white-space:nowrap;"
! Nr. || colspan=2 | Frequency (MHz) || L2 Cache || FSB (MHz)|| VT || colspan=2 | core Voltage (V) || colspan=2 | TDP (W) || ThinkPad Models
|- style="background:#ffdead;"
! !!max. !! min. !! !! !! !! high !! low !! high freq !! low freq !!
|-
| L7400 || 1500 || 1000 || 4MB || 667 || yes || 1.2 || 0.85 - 0.9 || 17 || ? || {{X60s}}, {{X60_Tablet}}
|-
| L7500 || 1600 || 800 || 4MB || 800 || yes || 1.1 || 0.85 - 0.9 || 17 || ? || {{X61s}}, {{X61_Tablet}}
|-
| L7700 || 1800 || 800 || 4MB || 800 || yes || 1.1 || 0.85 - 0.9 || 17 || ? || {{X61s}}, {{X61_Tablet}}
|-
| SL7100 || 1200 || 800 || 4MB || 800 || yes || 1.1 || 0.85 - 0.9 || 12 || ? || {{X300}}
|}

As you can see, the Low-Voltage CPU's work at the same Voltage as the normal CPUs when running in SLFM. With a simple tool (RMClock) you can use those lower voltages at every clock.
Intel gave other voltage-regions for the CPUs:

''the standard processor that works on a core voltage between 1.075V and 1.175V, the low voltage processors that work between 0.975V and 1.062V and finally the ultra low voltage processors that work between 0.80V and 0.975V.''

Intel doesn't think of the SLFM. With SLFM and a little bit luck, you're T-CPU can be thriftier than a LV-CPU but has more power.
With RMClock every T-CPU is thriftier than a LV-CPU, because you have the same voltage but a higher max-clock, so the sleep-states can be longer.

=Thermal Specifications=
The maximum temperature for safe operation is 100°C.

The catastrophic thermal protection temperature is 125°C.

Idle temperature is typically around 30-50°C.

Temperature at full utilisation is around 60-70°C.

These latter two values will of course depend largely on cooling systems and available airflow.

=Compiler optimisation flags=
==GCC==
In addition to the architecture independent <code>-O[0123s]</code> option hierarchy, architecture dependent optimisations are controlled by the <code>-march=<cpu-type></code> and <code>-mtune=<cpu-type></code> options. The <cpu-type> argument (not surprisingly) describes the type of cpu for which to optimise the compiled code. The <code>-mtune</code> option will generate code that is optimised for the given cpu type which will nevertheless run on cpu types other than the optimisation target. On the other hand, <code>-march</code> will attempt to optimise more aggressively at the expense of reducing portability to other cpu types. Optimisations implied by <code>-mtune</code> are a subset of <code>-march</code> optimisations, and thus it is only necessary to specify <code>-march</code> if the the maximum level of optimisation is desired.

With version of gcc before 4.3, 32-bit code should be compiled with the "prescott" as the cpu-type argument to <code>-march</code> or <code>-mtune</code> whereas 64-bit code should use the "nocona" argument. Gcc 4.3 however introduces "core2" as a valid argument to the <code>-mtune</code> and <code>-march</code> options which should be used. Alternatively, as of gcc 4.2, the "native" argument is supported. This will automatically determine the cpu-type on which compilation is taking place and apply optimisations specific to that cpu.

==Intel==
For the [http://www.spec.org/cpu2006/ SPEC CPU 2006 benchmarks], Intel used the shorthand <code>-fast</code>, which translates into <code>-O3 -ipo -static -no-prec-div -xP</code>. However, the compiler also provides the flag <code>-xT</code>, which activates the optimization for Core 2 Duo and SSSE3 (instead of SSE3 only with <code>-xP</code>).

=Microcode=
Much like software products, bugs, errata or ways to improve upon operation are often found in CPU's after they have reached the market. In some cases, the necessary changes can be applied by the end user without any change to the underlying hardware in the form of microcode updates downloadable from the manufacturer. Intel offers these microcode updates for download on their [http://downloadcenter.intel.com/Detail_Desc.aspx?ProductID=2676&DwnldID=14303&lang=eng website].

Provided the availability of the <tt>microcode</tt> and <tt>firmware</tt> kernel modules (which are enabled in the stock kernels of most distributions) and a suitable user space tool such as [http://urbanmyth.org/microcode/ microcode_ctl], one can install the updated microcode into their processors at runtime. The microcode update is volatile however, meaning that it disappears upon reboot. While this reduces the risk of applying such an update to essentially 0, it does mean that it must be applied on each boot.
==Debian==
You can install the microcode.ctl package which will take care of everything (including downloading the microcode itself) for you. Just run
{{cmdroot|aptitude install microcode.ctl}}. This package includes an init script which will run at boot to load the microcode into the processor. This script also contains a line which will remove the <tt>microcode</tt> kernel module once the operation is complete and it is no longer needed, however it is strangely commented out by default. If you want to keep your loaded modules (used memory) to a minimum, you can edit {{path|/etc/init.d/microcode.ctl}} and uncomment the line
<pre>
[ -x /sbin/modprobe ] && /sbin/modprobe -r microcode > /dev/null 2> /dev/null
</pre>
==Gentoo==
The <tt>microcode-ctl</tt> utility can be installed as follows: {{cmdroot|emerge microcode-ctl}}. This will create an init script <tt>/etc/init.d/microcode_ctl</tt>, but will not automatically set it to run on startup; to do so, run {{cmdroot|rc-update add microcode_ctl boot}}. Also, this will install an old copy of the microcode to <tt>/etc/microcode.dat</tt>; to update it, download a new copy from the link above and replace this file.

=Note on Hyper-Threading=
Note that as opposed to Pentium 4/NetBurst, current Core 2 do not support hyper-threading, and therefore there is usually no option in the BIOS to activate it. Refer to Intel's [http://www.intel.com/products/ht/hyperthreading_more.htm Hyper-Threading Technology] for a list of hyper-threading capable CPU.

=See also=
[[Intel_Core_Solo_(Yonah)|Intel Core Solo (Yonah)]]

[[Intel Core Duo (Yonah)]]

== External Links ==
*[http://www.intel.com/products/processor_number/chart/core2duo.htm Intel - Processor Numbers and Features]
*[http://en.wikipedia.org/wiki/List_of_Intel_Core_2_microprocessors#Mobile_processors Wikipedia - Intel Core 2 mobile microprocessors]

[[Category:Components]]

Intel Core 2 Duo (Merom)

2008-07-15T15:18:05Z

Notpeter: /* Features */

{| width="100%"
|style="vertical-align:top;padding-right:20px;width:10px;white-space:nowrap;" | __TOC__
|style="vertical-align:top" |
<div style="margin: 0; margin-right:10px; border: 1px solid #dfdfdf; padding: 0em 1em 1em 1em; background-color:#F8F8FF; align:right;">

The Intel 2 Core is the successor of the [[Intel Core Duo (Yonah)]] processor. Unlike the Yonah, the Merom was designed specifically with mobile applications in mind. The Merom introduced various architectural additions such as EM64T, [[SIMD|SSSE3]] and improved the performance by up to 25 percent. The 667 MHz FSB versions are part of the "Napa" platform, while the 800MHz FSB versions are part of the "Santa Rosa" platform. The chip is also part of the hardware from both the Centrino Duo and Centrino Pro brands.

=Features=
*Dual Core
*EM64T
*[Intel Virtualization Technoloy http://en.wikipedia.org/wiki/Vanderpool#Intel_Virtualization_Technology_.28Intel_VT.29]
*XD-Bit
*[[SIMD|MMX]], [[SIMD|SSE]], [[SIMD|SSE2]], [[SIMD|SSE3]], [[SIMD|SSSE3]] instruction sets
*667 or 800 MHz FSB
*65 nm fabrication process
*4 MB or 2 MB L2-Cache with dynamic cache sizing
*[[SpeedStep|Enhanced Intel SpeedStep (EIST)]], power states: normal (C0), AutoHALT/MWAIT (C1), Stop Grant (C2), Deep Sleep (C3), [[QuickStart and Deeper Sleep|Deeper Sleep]] (C4)
</div>
|}

=Available Types and ThinkPads featuring them=
==Standard Voltage==
{| border=1 cellspacing=0 cellpadding=2
|- style="background:#ffdead;white-space:nowrap;"
! Nr. || colspan=2 | Frequency (MHz) || L2 Cache || FSB (MHz)|| VT || colspan=2 | core Voltage (V) || colspan=2 | TDP (W) || ThinkPad Models
|- style="background:#ffdead;"
! !!max. !! min. !! !! !! !! high !! low !! high freq !! low freq !!
|-
| T8300 || 2400 || 800 || 3MB || 800 || yes || 1.25 || 1 ? || ? || ? || {{X61}}
|-
| T7800 || 2600 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{T61p}}
|-
| T7700 || 2400 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}, {{T61p}}
|-
| T7600 || 2333 || 1000 || 4MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{T60}}, {{T60p}}
|-
| T7500 || 2200 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}, {{X61}}
|-
| T7400 || 2166 || 1000 || 4MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{T60}}, {{T60p}}, {{Z61t}}
|-
| T7300 || 2000 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}, {{X61}}
|-
| T7200 || 2000 || 1000 || 4MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{R60}}, {{T60}}, {{X60}}, {{Z61m}}, {{Z61t}}
|-
| T7100 || 1800 || 1000 || 2MB || 800 || yes || ? || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}
|-
| T5600 || 1833 || 1000 || 2MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{R60}}, {{T60}}, {{X60}}, {{Z61t}}
|-
| T5500 || 1666 || 1000 || 2MB || 667 || no || 1.30 || 0.95 || 34 || 20 || {{R60}}, {{T60}}, {{X60}}, {{Z61m}}, {{Z61t}}
|}

==Low Voltage==
{| border=1 cellspacing=0 cellpadding=2
|- style="background:#ffdead;white-space:nowrap;"
! Nr. || colspan=2 | Frequency (MHz) || L2 Cache || FSB (MHz)|| VT || colspan=2 | core Voltage (V) || colspan=2 | TDP (W) || ThinkPad Models
|- style="background:#ffdead;"
! !!max. !! min. !! !! !! !! high !! low !! high freq !! low freq !!
|-
| L7400 || 1500 || 1000 || 4MB || 667 || yes || 1.2 || 0.85 - 0.9 || 17 || ? || {{X60s}}, {{X60_Tablet}}
|-
| L7500 || 1600 || 800 || 4MB || 800 || yes || 1.1 || 0.85 - 0.9 || 17 || ? || {{X61s}}, {{X61_Tablet}}
|-
| L7700 || 1800 || 800 || 4MB || 800 || yes || 1.1 || 0.85 - 0.9 || 17 || ? || {{X61s}}, {{X61_Tablet}}
|-
| SL7100 || 1200 || 800 || 4MB || 800 || yes || 1.1 || 0.85 - 0.9 || 12 || ? || {{X300}}
|}

As you can see, the Low-Voltage CPU's work at the same Voltage as the normal CPUs when running in SLFM. With a simple tool (RMClock) you can use those lower voltages at every clock.
Intel gave other voltage-regions for the CPUs:

''the standard processor that works on a core voltage between 1.075V and 1.175V, the low voltage processors that work between 0.975V and 1.062V and finally the ultra low voltage processors that work between 0.80V and 0.975V.''

Intel doesn't think of the SLFM. With SLFM and a little bit luck, you're T-CPU can be thriftier than a LV-CPU but has more power.
With RMClock every T-CPU is thriftier than a LV-CPU, because you have the same voltage but a higher max-clock, so the sleep-states can be longer.

=Thermal Specifications=
The maximum temperature for safe operation is 100°C.

The catastrophic thermal protection temperature is 125°C.

Idle temperature is typically around 30-50°C.

Temperature at full utilisation is around 60-70°C.

These latter two values will of course depend largely on cooling systems and available airflow.

=Compiler optimisation flags=
==GCC==
In addition to the architecture independent <code>-O[0123s]</code> option hierarchy, architecture dependent optimisations are controlled by the <code>-march=<cpu-type></code> and <code>-mtune=<cpu-type></code> options. The <cpu-type> argument (not surprisingly) describes the type of cpu for which to optimise the compiled code. The <code>-mtune</code> option will generate code that is optimised for the given cpu type which will nevertheless run on cpu types other than the optimisation target. On the other hand, <code>-march</code> will attempt to optimise more aggressively at the expense of reducing portability to other cpu types. Optimisations implied by <code>-mtune</code> are a subset of <code>-march</code> optimisations, and thus it is only necessary to specify <code>-march</code> if the the maximum level of optimisation is desired.

With version of gcc before 4.3, 32-bit code should be compiled with the "prescott" as the cpu-type argument to <code>-march</code> or <code>-mtune</code> whereas 64-bit code should use the "nocona" argument. Gcc 4.3 however introduces "core2" as a valid argument to the <code>-mtune</code> and <code>-march</code> options which should be used. Alternatively, as of gcc 4.2, the "native" argument is supported. This will automatically determine the cpu-type on which compilation is taking place and apply optimisations specific to that cpu.

==Intel==
For the [http://www.spec.org/cpu2006/ SPEC CPU 2006 benchmarks], Intel used the shorthand <code>-fast</code>, which translates into <code>-O3 -ipo -static -no-prec-div -xP</code>. However, the compiler also provides the flag <code>-xT</code>, which activates the optimization for Core 2 Duo and SSSE3 (instead of SSE3 only with <code>-xP</code>).

=Microcode=
Much like software products, bugs, errata or ways to improve upon operation are often found in CPU's after they have reached the market. In some cases, the necessary changes can be applied by the end user without any change to the underlying hardware in the form of microcode updates downloadable from the manufacturer. Intel offers these microcode updates for download on their [http://downloadcenter.intel.com/Detail_Desc.aspx?ProductID=2676&DwnldID=14303&lang=eng website].

Provided the availability of the <tt>microcode</tt> and <tt>firmware</tt> kernel modules (which are enabled in the stock kernels of most distributions) and a suitable user space tool such as [http://urbanmyth.org/microcode/ microcode_ctl], one can install the updated microcode into their processors at runtime. The microcode update is volatile however, meaning that it disappears upon reboot. While this reduces the risk of applying such an update to essentially 0, it does mean that it must be applied on each boot.
==Debian==
You can install the microcode.ctl package which will take care of everything (including downloading the microcode itself) for you. Just run
{{cmdroot|aptitude install microcode.ctl}}. This package includes an init script which will run at boot to load the microcode into the processor. This script also contains a line which will remove the <tt>microcode</tt> kernel module once the operation is complete and it is no longer needed, however it is strangely commented out by default. If you want to keep your loaded modules (used memory) to a minimum, you can edit {{path|/etc/init.d/microcode.ctl}} and uncomment the line
<pre>
[ -x /sbin/modprobe ] && /sbin/modprobe -r microcode > /dev/null 2> /dev/null
</pre>
==Gentoo==
The <tt>microcode-ctl</tt> utility can be installed as follows: {{cmdroot|emerge microcode-ctl}}. This will create an init script <tt>/etc/init.d/microcode_ctl</tt>, but will not automatically set it to run on startup; to do so, run {{cmdroot|rc-update add microcode_ctl boot}}. Also, this will install an old copy of the microcode to <tt>/etc/microcode.dat</tt>; to update it, download a new copy from the link above and replace this file.

=Note on Hyper-Threading=
Note that as opposed to Pentium 4/NetBurst, current Core 2 do not support hyper-threading, and therefore there is usually no option in the BIOS to activate it. Refer to Intel's [http://www.intel.com/products/ht/hyperthreading_more.htm Hyper-Threading Technology] for a list of hyper-threading capable CPU.

=See also=
[[Intel_Core_Solo_(Yonah)|Intel Core Solo (Yonah)]]

[[Intel Core Duo (Yonah)]]

== External Links ==
*[http://www.intel.com/products/processor_number/chart/core2duo.htm Intel - Processor Numbers and Features]
*[http://en.wikipedia.org/wiki/List_of_Intel_Core_2_microprocessors#Mobile_processors Wikipedia - Intel Core 2 mobile microprocessors]

[[Category:Components]]

Intel Core 2 Duo (Merom)

2008-07-15T15:16:05Z

Notpeter: /* Features */ Wikipedia link fix, (section header name change)

{| width="100%"
|style="vertical-align:top;padding-right:20px;width:10px;white-space:nowrap;" | __TOC__
|style="vertical-align:top" |
<div style="margin: 0; margin-right:10px; border: 1px solid #dfdfdf; padding: 0em 1em 1em 1em; background-color:#F8F8FF; align:right;">

The Intel 2 Core is the successor of the [[Intel Core Duo (Yonah)]] processor. Unlike the Yonah, the Merom was designed specifically with mobile applications in mind. The Merom introduced various architectural additions such as EM64T, [[SIMD|SSSE3]] and improved the performance by up to 25 percent. The 667 MHz FSB versions are part of the "Napa" platform, while the 800MHz FSB versions are part of the "Santa Rosa" platform. The chip is also part of the hardware from both the Centrino Duo and Centrino Pro brands.

=Features=
*Dual Core
*EM64T
*[http://en.wikipedia.org/wiki/Vanderpool#Intel_Virtualization_Technology_.28Intel_VT.29]
*XD-Bit
*[[SIMD|MMX]], [[SIMD|SSE]], [[SIMD|SSE2]], [[SIMD|SSE3]], [[SIMD|SSSE3]] instruction sets
*667 or 800 MHz FSB
*65 nm fabrication process
*4 MB or 2 MB L2-Cache with dynamic cache sizing
*[[SpeedStep|Enhanced Intel SpeedStep (EIST)]], power states: normal (C0), AutoHALT/MWAIT (C1), Stop Grant (C2), Deep Sleep (C3), [[QuickStart and Deeper Sleep|Deeper Sleep]] (C4)
</div>
|}

=Available Types and ThinkPads featuring them=
==Standard Voltage==
{| border=1 cellspacing=0 cellpadding=2
|- style="background:#ffdead;white-space:nowrap;"
! Nr. || colspan=2 | Frequency (MHz) || L2 Cache || FSB (MHz)|| VT || colspan=2 | core Voltage (V) || colspan=2 | TDP (W) || ThinkPad Models
|- style="background:#ffdead;"
! !!max. !! min. !! !! !! !! high !! low !! high freq !! low freq !!
|-
| T8300 || 2400 || 800 || 3MB || 800 || yes || 1.25 || 1 ? || ? || ? || {{X61}}
|-
| T7800 || 2600 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{T61p}}
|-
| T7700 || 2400 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}, {{T61p}}
|-
| T7600 || 2333 || 1000 || 4MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{T60}}, {{T60p}}
|-
| T7500 || 2200 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}, {{X61}}
|-
| T7400 || 2166 || 1000 || 4MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{T60}}, {{T60p}}, {{Z61t}}
|-
| T7300 || 2000 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}, {{X61}}
|-
| T7200 || 2000 || 1000 || 4MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{R60}}, {{T60}}, {{X60}}, {{Z61m}}, {{Z61t}}
|-
| T7100 || 1800 || 1000 || 2MB || 800 || yes || ? || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}
|-
| T5600 || 1833 || 1000 || 2MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{R60}}, {{T60}}, {{X60}}, {{Z61t}}
|-
| T5500 || 1666 || 1000 || 2MB || 667 || no || 1.30 || 0.95 || 34 || 20 || {{R60}}, {{T60}}, {{X60}}, {{Z61m}}, {{Z61t}}
|}

==Low Voltage==
{| border=1 cellspacing=0 cellpadding=2
|- style="background:#ffdead;white-space:nowrap;"
! Nr. || colspan=2 | Frequency (MHz) || L2 Cache || FSB (MHz)|| VT || colspan=2 | core Voltage (V) || colspan=2 | TDP (W) || ThinkPad Models
|- style="background:#ffdead;"
! !!max. !! min. !! !! !! !! high !! low !! high freq !! low freq !!
|-
| L7400 || 1500 || 1000 || 4MB || 667 || yes || 1.2 || 0.85 - 0.9 || 17 || ? || {{X60s}}, {{X60_Tablet}}
|-
| L7500 || 1600 || 800 || 4MB || 800 || yes || 1.1 || 0.85 - 0.9 || 17 || ? || {{X61s}}, {{X61_Tablet}}
|-
| L7700 || 1800 || 800 || 4MB || 800 || yes || 1.1 || 0.85 - 0.9 || 17 || ? || {{X61s}}, {{X61_Tablet}}
|-
| SL7100 || 1200 || 800 || 4MB || 800 || yes || 1.1 || 0.85 - 0.9 || 12 || ? || {{X300}}
|}

As you can see, the Low-Voltage CPU's work at the same Voltage as the normal CPUs when running in SLFM. With a simple tool (RMClock) you can use those lower voltages at every clock.
Intel gave other voltage-regions for the CPUs:

''the standard processor that works on a core voltage between 1.075V and 1.175V, the low voltage processors that work between 0.975V and 1.062V and finally the ultra low voltage processors that work between 0.80V and 0.975V.''

Intel doesn't think of the SLFM. With SLFM and a little bit luck, you're T-CPU can be thriftier than a LV-CPU but has more power.
With RMClock every T-CPU is thriftier than a LV-CPU, because you have the same voltage but a higher max-clock, so the sleep-states can be longer.

=Thermal Specifications=
The maximum temperature for safe operation is 100°C.

The catastrophic thermal protection temperature is 125°C.

Idle temperature is typically around 30-50°C.

Temperature at full utilisation is around 60-70°C.

These latter two values will of course depend largely on cooling systems and available airflow.

=Compiler optimisation flags=
==GCC==
In addition to the architecture independent <code>-O[0123s]</code> option hierarchy, architecture dependent optimisations are controlled by the <code>-march=<cpu-type></code> and <code>-mtune=<cpu-type></code> options. The <cpu-type> argument (not surprisingly) describes the type of cpu for which to optimise the compiled code. The <code>-mtune</code> option will generate code that is optimised for the given cpu type which will nevertheless run on cpu types other than the optimisation target. On the other hand, <code>-march</code> will attempt to optimise more aggressively at the expense of reducing portability to other cpu types. Optimisations implied by <code>-mtune</code> are a subset of <code>-march</code> optimisations, and thus it is only necessary to specify <code>-march</code> if the the maximum level of optimisation is desired.

With version of gcc before 4.3, 32-bit code should be compiled with the "prescott" as the cpu-type argument to <code>-march</code> or <code>-mtune</code> whereas 64-bit code should use the "nocona" argument. Gcc 4.3 however introduces "core2" as a valid argument to the <code>-mtune</code> and <code>-march</code> options which should be used. Alternatively, as of gcc 4.2, the "native" argument is supported. This will automatically determine the cpu-type on which compilation is taking place and apply optimisations specific to that cpu.

==Intel==
For the [http://www.spec.org/cpu2006/ SPEC CPU 2006 benchmarks], Intel used the shorthand <code>-fast</code>, which translates into <code>-O3 -ipo -static -no-prec-div -xP</code>. However, the compiler also provides the flag <code>-xT</code>, which activates the optimization for Core 2 Duo and SSSE3 (instead of SSE3 only with <code>-xP</code>).

=Microcode=
Much like software products, bugs, errata or ways to improve upon operation are often found in CPU's after they have reached the market. In some cases, the necessary changes can be applied by the end user without any change to the underlying hardware in the form of microcode updates downloadable from the manufacturer. Intel offers these microcode updates for download on their [http://downloadcenter.intel.com/Detail_Desc.aspx?ProductID=2676&DwnldID=14303&lang=eng website].

Provided the availability of the <tt>microcode</tt> and <tt>firmware</tt> kernel modules (which are enabled in the stock kernels of most distributions) and a suitable user space tool such as [http://urbanmyth.org/microcode/ microcode_ctl], one can install the updated microcode into their processors at runtime. The microcode update is volatile however, meaning that it disappears upon reboot. While this reduces the risk of applying such an update to essentially 0, it does mean that it must be applied on each boot.
==Debian==
You can install the microcode.ctl package which will take care of everything (including downloading the microcode itself) for you. Just run
{{cmdroot|aptitude install microcode.ctl}}. This package includes an init script which will run at boot to load the microcode into the processor. This script also contains a line which will remove the <tt>microcode</tt> kernel module once the operation is complete and it is no longer needed, however it is strangely commented out by default. If you want to keep your loaded modules (used memory) to a minimum, you can edit {{path|/etc/init.d/microcode.ctl}} and uncomment the line
<pre>
[ -x /sbin/modprobe ] && /sbin/modprobe -r microcode > /dev/null 2> /dev/null
</pre>
==Gentoo==
The <tt>microcode-ctl</tt> utility can be installed as follows: {{cmdroot|emerge microcode-ctl}}. This will create an init script <tt>/etc/init.d/microcode_ctl</tt>, but will not automatically set it to run on startup; to do so, run {{cmdroot|rc-update add microcode_ctl boot}}. Also, this will install an old copy of the microcode to <tt>/etc/microcode.dat</tt>; to update it, download a new copy from the link above and replace this file.

=Note on Hyper-Threading=
Note that as opposed to Pentium 4/NetBurst, current Core 2 do not support hyper-threading, and therefore there is usually no option in the BIOS to activate it. Refer to Intel's [http://www.intel.com/products/ht/hyperthreading_more.htm Hyper-Threading Technology] for a list of hyper-threading capable CPU.

=See also=
[[Intel_Core_Solo_(Yonah)|Intel Core Solo (Yonah)]]

[[Intel Core Duo (Yonah)]]

== External Links ==
*[http://www.intel.com/products/processor_number/chart/core2duo.htm Intel - Processor Numbers and Features]
*[http://en.wikipedia.org/wiki/List_of_Intel_Core_2_microprocessors#Mobile_processors Wikipedia - Intel Core 2 mobile microprocessors]

[[Category:Components]]

Intel Core 2 Duo (Merom)

2008-07-15T15:11:03Z

Notpeter: /* Low Voltage */ Added TDP for X300's SL7100

{| width="100%"
|style="vertical-align:top;padding-right:20px;width:10px;white-space:nowrap;" | __TOC__
|style="vertical-align:top" |
<div style="margin: 0; margin-right:10px; border: 1px solid #dfdfdf; padding: 0em 1em 1em 1em; background-color:#F8F8FF; align:right;">

The Intel 2 Core is the successor of the [[Intel Core Duo (Yonah)]] processor. Unlike the Yonah, the Merom was designed specifically with mobile applications in mind. The Merom introduced various architectural additions such as EM64T, [[SIMD|SSSE3]] and improved the performance by up to 25 percent. The 667 MHz FSB versions are part of the "Napa" platform, while the 800MHz FSB versions are part of the "Santa Rosa" platform. The chip is also part of the hardware from both the Centrino Duo and Centrino Pro brands.

=Features=
*Dual Core
*EM64T
*[http://en.wikipedia.org/wiki/Vanderpool#Intel_VT_.28IVT.29 Intel Virtualization Technology]
*XD-Bit
*[[SIMD|MMX]], [[SIMD|SSE]], [[SIMD|SSE2]], [[SIMD|SSE3]], [[SIMD|SSSE3]] instruction sets
*667 or 800 MHz FSB
*65 nm fabrication process
*4 MB or 2 MB L2-Cache with dynamic cache sizing
*[[SpeedStep|Enhanced Intel SpeedStep (EIST)]], power states: normal (C0), AutoHALT/MWAIT (C1), Stop Grant (C2), Deep Sleep (C3), [[QuickStart and Deeper Sleep|Deeper Sleep]] (C4)
</div>
|}

=Available Types and ThinkPads featuring them=
==Standard Voltage==
{| border=1 cellspacing=0 cellpadding=2
|- style="background:#ffdead;white-space:nowrap;"
! Nr. || colspan=2 | Frequency (MHz) || L2 Cache || FSB (MHz)|| VT || colspan=2 | core Voltage (V) || colspan=2 | TDP (W) || ThinkPad Models
|- style="background:#ffdead;"
! !!max. !! min. !! !! !! !! high !! low !! high freq !! low freq !!
|-
| T8300 || 2400 || 800 || 3MB || 800 || yes || 1.25 || 1 ? || ? || ? || {{X61}}
|-
| T7800 || 2600 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{T61p}}
|-
| T7700 || 2400 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}, {{T61p}}
|-
| T7600 || 2333 || 1000 || 4MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{T60}}, {{T60p}}
|-
| T7500 || 2200 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}, {{X61}}
|-
| T7400 || 2166 || 1000 || 4MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{T60}}, {{T60p}}, {{Z61t}}
|-
| T7300 || 2000 || 1000 || 4MB || 800 || yes || 1.30 || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}, {{X61}}
|-
| T7200 || 2000 || 1000 || 4MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{R60}}, {{T60}}, {{X60}}, {{Z61m}}, {{Z61t}}
|-
| T7100 || 1800 || 1000 || 2MB || 800 || yes || ? || 0.85-0.9 || 35 || ? || {{R61}}, {{T61}}
|-
| T5600 || 1833 || 1000 || 2MB || 667 || yes || 1.30 || 0.95 || 34 || 20 || {{R60}}, {{T60}}, {{X60}}, {{Z61t}}
|-
| T5500 || 1666 || 1000 || 2MB || 667 || no || 1.30 || 0.95 || 34 || 20 || {{R60}}, {{T60}}, {{X60}}, {{Z61m}}, {{Z61t}}
|}

==Low Voltage==
{| border=1 cellspacing=0 cellpadding=2
|- style="background:#ffdead;white-space:nowrap;"
! Nr. || colspan=2 | Frequency (MHz) || L2 Cache || FSB (MHz)|| VT || colspan=2 | core Voltage (V) || colspan=2 | TDP (W) || ThinkPad Models
|- style="background:#ffdead;"
! !!max. !! min. !! !! !! !! high !! low !! high freq !! low freq !!
|-
| L7400 || 1500 || 1000 || 4MB || 667 || yes || 1.2 || 0.85 - 0.9 || 17 || ? || {{X60s}}, {{X60_Tablet}}
|-
| L7500 || 1600 || 800 || 4MB || 800 || yes || 1.1 || 0.85 - 0.9 || 17 || ? || {{X61s}}, {{X61_Tablet}}
|-
| L7700 || 1800 || 800 || 4MB || 800 || yes || 1.1 || 0.85 - 0.9 || 17 || ? || {{X61s}}, {{X61_Tablet}}
|-
| SL7100 || 1200 || 800 || 4MB || 800 || yes || 1.1 || 0.85 - 0.9 || 12 || ? || {{X300}}
|}

As you can see, the Low-Voltage CPU's work at the same Voltage as the normal CPUs when running in SLFM. With a simple tool (RMClock) you can use those lower voltages at every clock.
Intel gave other voltage-regions for the CPUs:

''the standard processor that works on a core voltage between 1.075V and 1.175V, the low voltage processors that work between 0.975V and 1.062V and finally the ultra low voltage processors that work between 0.80V and 0.975V.''

Intel doesn't think of the SLFM. With SLFM and a little bit luck, you're T-CPU can be thriftier than a LV-CPU but has more power.
With RMClock every T-CPU is thriftier than a LV-CPU, because you have the same voltage but a higher max-clock, so the sleep-states can be longer.

=Thermal Specifications=
The maximum temperature for safe operation is 100°C.

The catastrophic thermal protection temperature is 125°C.

Idle temperature is typically around 30-50°C.

Temperature at full utilisation is around 60-70°C.

These latter two values will of course depend largely on cooling systems and available airflow.

=Compiler optimisation flags=
==GCC==
In addition to the architecture independent <code>-O[0123s]</code> option hierarchy, architecture dependent optimisations are controlled by the <code>-march=<cpu-type></code> and <code>-mtune=<cpu-type></code> options. The <cpu-type> argument (not surprisingly) describes the type of cpu for which to optimise the compiled code. The <code>-mtune</code> option will generate code that is optimised for the given cpu type which will nevertheless run on cpu types other than the optimisation target. On the other hand, <code>-march</code> will attempt to optimise more aggressively at the expense of reducing portability to other cpu types. Optimisations implied by <code>-mtune</code> are a subset of <code>-march</code> optimisations, and thus it is only necessary to specify <code>-march</code> if the the maximum level of optimisation is desired.

With version of gcc before 4.3, 32-bit code should be compiled with the "prescott" as the cpu-type argument to <code>-march</code> or <code>-mtune</code> whereas 64-bit code should use the "nocona" argument. Gcc 4.3 however introduces "core2" as a valid argument to the <code>-mtune</code> and <code>-march</code> options which should be used. Alternatively, as of gcc 4.2, the "native" argument is supported. This will automatically determine the cpu-type on which compilation is taking place and apply optimisations specific to that cpu.

==Intel==
For the [http://www.spec.org/cpu2006/ SPEC CPU 2006 benchmarks], Intel used the shorthand <code>-fast</code>, which translates into <code>-O3 -ipo -static -no-prec-div -xP</code>. However, the compiler also provides the flag <code>-xT</code>, which activates the optimization for Core 2 Duo and SSSE3 (instead of SSE3 only with <code>-xP</code>).

=Microcode=
Much like software products, bugs, errata or ways to improve upon operation are often found in CPU's after they have reached the market. In some cases, the necessary changes can be applied by the end user without any change to the underlying hardware in the form of microcode updates downloadable from the manufacturer. Intel offers these microcode updates for download on their [http://downloadcenter.intel.com/Detail_Desc.aspx?ProductID=2676&DwnldID=14303&lang=eng website].

Provided the availability of the <tt>microcode</tt> and <tt>firmware</tt> kernel modules (which are enabled in the stock kernels of most distributions) and a suitable user space tool such as [http://urbanmyth.org/microcode/ microcode_ctl], one can install the updated microcode into their processors at runtime. The microcode update is volatile however, meaning that it disappears upon reboot. While this reduces the risk of applying such an update to essentially 0, it does mean that it must be applied on each boot.
==Debian==
You can install the microcode.ctl package which will take care of everything (including downloading the microcode itself) for you. Just run
{{cmdroot|aptitude install microcode.ctl}}. This package includes an init script which will run at boot to load the microcode into the processor. This script also contains a line which will remove the <tt>microcode</tt> kernel module once the operation is complete and it is no longer needed, however it is strangely commented out by default. If you want to keep your loaded modules (used memory) to a minimum, you can edit {{path|/etc/init.d/microcode.ctl}} and uncomment the line
<pre>
[ -x /sbin/modprobe ] && /sbin/modprobe -r microcode > /dev/null 2> /dev/null
</pre>
==Gentoo==
The <tt>microcode-ctl</tt> utility can be installed as follows: {{cmdroot|emerge microcode-ctl}}. This will create an init script <tt>/etc/init.d/microcode_ctl</tt>, but will not automatically set it to run on startup; to do so, run {{cmdroot|rc-update add microcode_ctl boot}}. Also, this will install an old copy of the microcode to <tt>/etc/microcode.dat</tt>; to update it, download a new copy from the link above and replace this file.

=Note on Hyper-Threading=
Note that as opposed to Pentium 4/NetBurst, current Core 2 do not support hyper-threading, and therefore there is usually no option in the BIOS to activate it. Refer to Intel's [http://www.intel.com/products/ht/hyperthreading_more.htm Hyper-Threading Technology] for a list of hyper-threading capable CPU.

=See also=
[[Intel_Core_Solo_(Yonah)|Intel Core Solo (Yonah)]]

[[Intel Core Duo (Yonah)]]

== External Links ==
*[http://www.intel.com/products/processor_number/chart/core2duo.htm Intel - Processor Numbers and Features]
*[http://en.wikipedia.org/wiki/List_of_Intel_Core_2_microprocessors#Mobile_processors Wikipedia - Intel Core 2 mobile microprocessors]

[[Category:Components]]

ThinkPad Button

2008-06-09T00:44:48Z

Notpeter: Added X300 (labelled ThinkVantage)

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The ThinkPad Button is a button situated in the upper left corner of the keyboard on modern ThinkPads. It is intended to be a means of quick access to help and support. Technically it is nothing else than a button that can be configured to launch a certain piece of software. While originally it was grey and labelled {{ibmkey|ThinkPad|#494949}}, IBM later made it blue and called it the {{ibmkey|Access IBM|#495988}} Button. Lenovo relabelled it as {{ibmkey|ThinkVantage|#495988}} after it took over the ThinkPad line from IBM.
</div>
|}
__NOTOC__
== System Boot ==
Pressing {{ibmkey|Access IBM|#495988}} or {{ibmkey|ThinkVantage|#495988}} at system boot can launch the [[Predesktop Area| Predesktop Area]]. This depends on a specific setting of the BIOS Setup Utility and on the availability of either a [[Hidden Protected Area|Hidden Protected Area]] or a [[Rescue and Recovery|Rescue and Recovery partition]]. See the linked pages for details.

== Linux support ==
===Using tpb===
Under Linux, the IBM ThinkPad(tm) special keys can be enabled using [[tpb]].

I.e., to make pressing the Access IBM Button launch ntpctl, add the following line {{path|/etc/tpbrc}} file:
THINKPAD /usr/bin/X11/xterm -T ntpctl -e ntpctl

To make pressing the Access IBM Button launch the ThinkWiki homepage in Firefox, add the following line:
<nowiki>THINKPAD /usr/bin/firefox http://www.thinkwiki.org</nowiki>

See the [[tpb]] page and the [[How to get special keys to work | ThinkPad special keys HOWTO]] for more information.

===Using KDE===

KDE supports assigning actions to (some) ThinkPad special keys, through the ThinkPad buttons [[KMilo]] plugin.

It can be activated and configured in the KDE Control Center (<tt>kcontrol</tt>), under <tt>System Administration --> IBM Thinkpad Laptop</tt>.

===Using xbindkeys on Ubuntu===

On Ubuntu (at least 7.04/Feisty) <code>tpb</code> is not really an option, because it conflicts with <code>hotkey-setup</code>, which is responsible for much things working out of the box.

An alternative is to use <code>xbindkeys</code>, which can easily be installed with <code>aptitude install xbindkeys</code> or via the Synaptic package manager. It can be used to assign arbitrary commands to certain keycodes. Therefore, we first have to find this keycode by running <code>xbindkeys --key</code> and pressing the ThinkPad Button. This should result in something like the following:
sean@amalthea ~ $ xbindkeys --key
Press combination of keys or/and click under the window.
You can use one of the two lines after "NoCommand"
in $HOME/.xbindkeysrc to bind a key.
"NoCommand"
m:0x0 + c:159
NoSymbol

Now we can construct a minimal configuration file in <code>~/.xbindkeysrc</code>:
"gnome-terminal"
m:0x0 + c:159
After starting <code>xbindkeys</code> without further options the ThinkPad Button should launch a new terminal.

To start the program automatically at login add it under "System -> Preferences -> Sessions -> Startup Programs" (assuming the Gnome Desktop is used, otherwise add it to your <code>~/.xinitrc</code>, <code>~/.xsession</code> or whatever is responsible for startup items in your setting).

===Using Gnome===

A simpler but less flexible possibility than <code>xbindkeys</code> is "System -> Preferences -> Keyboard Shortcuts". Just go to (for example) "Run a terminal" and press the ThinkPad Button, when asked for a "New accelerator...". This will only work under the Gnome Desktop and cannot execute arbitrary commands, as <code>xbindkeys</code> and <code>tpb</code> can.

== Windows support (2000 or XP) ==
If you want to customize the program that is launched when the {{ibmkey|ThinkPad|#494949}}, {{ibmkey|Access IBM|#495988}} or {{ibmkey|ThinkVantage|#495988}} button is pressed while
the machine is running {{Windows}} (2000 or XP) you can change the following registry entry:

<code>HKEY_LOCAL_MACHINE\SOFTWARE\IBM\TPHOTKEY\8001</code>

Here are the default values for the original IBM version:

[HKEY_LOCAL_MACHINE\SOFTWARE\IBM\TPHOTKEY\8001]
"File"="C:\\Program Files\\IBM\\Access IBM\\aibm.exe"
"DispName"="Access IBM"

And these are the default values for the Lenovo version:

[HKEY_LOCAL_MACHINE\SOFTWARE\IBM\TPHOTKEY\8001]
"File"="C:\\PROGRA~1\\THINKV~1\\PrdCtr\\LPL1.exe"

== Related Links ==
*[[Python script for Windows to control ThinkPad features]] that also allows querying of the ThinkPad button
*[http://www.pc.ibm.com/us/think/thinkvantagetech/accessibm.html IBMs Access IBM ThinkVantage Technology page]
*[http://www-3.ibm.com/pc/support/site.wss/AIBM-TOOLS.html Access IBM - Customization Guide]

==Models featuring this Technology==
'''"ThinkPad" button'''
*ThinkPad {{A Series}}
*ThinkPad {{R30}}, {{R31}}, {{R32}}
*ThinkPad {{T20}}, {{T21}}, {{T22}}, {{T23}}, {{T30}}
*ThinkPad {{X20}}, {{X21}}, {{X22}}, {{X23}}, {{X24}}, {{X30}}
*ThinkPad {{TransNote}}
*ThinkPad {{S30}}, {{S31}}

'''"Access IBM" button'''
*ThinkPad {{G40}}, {{G41}}
*ThinkPad {{R40}}, {{R40e}}, {{R50}}, {{R50e}}, {{R50p}}, {{R51}}, {{R51e}}, {{R52}}
*ThinkPad {{T40}}, {{T40p}}, {{T41}}, {{T41p}}, {{T42}}, {{T42p}}, {{T43}}, {{T43p}}
*ThinkPad {{X31}}, {{X32}}, {{X40}}, {{X41}}, {{X41T}}

'''"ThinkVantage" button'''
*ThinkPad {{R60}}, {{R60e}}, {{R61}}
*ThinkPad {{T60}}, {{T60p}}, {{T61}}
*ThinkPad {{X60}}, {{X60s}}, {{X61s}}, {{X61_Tablet}}, {{X300}}
*ThinkPad {{Z Series}}

[[Category:Glossary]]