(I'm putting this in Talk until it can be wikified for the article. Zuzu 15:18, 17 September 2007 (UTC) )
I got rid of the memory stability problem by disabling the 32M PC66 memeory that is built in the motherboard. I found out that byte 2B of CMOS controls the SDRAM banks. Bit b0 disables internal 32M memory. By changing the content from 80 -> 81 the 32M is disabled.
Now I have two 128 Sodimms working fine. No need more to seek for cas3.
2B is row 20 column B in the editor inside the BIOS config - see pkiff's reply
PostPosted: Tue Nov 28, 2006 2:17 pm Post subject: Reply with quote Some 600E and 770X machines apparently shipped with a BIOS setting of "00" at byte 20 instead of "02". This means that for some reason there are 600/770 machines that have a particular bit turned on by default and other 600/770 machines don't. I don't know what that particular bit controls or why some machines might have it on by default and others off.
From what I've seen, there have been no reported problems from people who have changed byte 20 to from "00" to "0A" instead of from "02" to "0A". Having said that, I personally would try to retain the original BIOS settings as much as possible if it were my machine. So I would recommend changing "00" to "08" -- this will turn on the bit that controls the L2 cache without making any other changes. If you change "00" to "0A" you are actually turning on TWO bits: one controls the L2 cache and the other serves some unknown function.
This was exactly the situation I was in. Also, after rebooting, dmesg in Linux still reports a 330MHz Pentium II. Zuzu 21:44, 6 October 2007 (UTC)
I checked modifying manually the following bytes/bits from CMOS which are propably dealing with cache
2CH FD -> BD -- disable internal cache 2DH 10 -> 14 -- disable internal cache 3BH 0 -> 03 -- enable internal and external cache
None of them help. So I am starting to believe, that the problem is inside the IBM bios code setting up the caches in a PII way instead of PIII way.
I don't know if your machine has the same bios than mine 600E. Anyway, this is how I do in my 600E.
When you boot, you get bios post error 127. Then you shoud do the following:
Choose "test", choose "exit", choose "config", hit "ctrl-d", opens bios hex-editor. Take cursor to position 20, key "02" -> "0A", hit "F2", hit "esc", choose "exit", choose "ok", and reboot.
Next boot should go without error-127
The hex-editor calculates the checksum automatically.
In case you edit the bios data and the machine doesn't boot correctly, you can always reset the CMOS data by taking out the bios cmos battery for 30 seconds. After that the next boot will preset it to initial values (you have to set the time also).
Article needed for MMC-2 CPU cards
hat's right. I put the code in GRUB. The speedstep mod and the level 2 cache can be enabled before booting an operating system.
Being a Linux user, I have not been satisfied with the existing solutions to enable the speedstep mod. The kernel module by wmarcusm is great but has one problem. Since it does not change the kernel's internal variables like loops_per_jiffies, time-related tasks can malfunction. If you do 'sleep(1)', it actually sleeps less than 1 second. I do a lot of timing-sensitive stuff, so it is a real problem for me.
The tsc is not recalibrated either. To make everything work properly, the kernel source has to be modified. But, if you have no problem giving up tsc, it is possible to add "clock=pit" to the kernel boot options. Then you only need to update loops_per_jiffies or cpu_data.loops_per_jiffies, which can be done in a kernel module.
But I wanted to use tsc as the time base and did not want to patch and recompile the kernel everytime I install a new kernel. So I put them in the boot loader, GRUB.
I am not using Windows, but if you do, it will activate the mod and enable the cache before Windows loads. It will also activate the mod/l2cache when waking up from WinXP hibernation. (If APM hibernation is used, it won't work, as APM hibernation/wakeup is implemented in BIOS and bypasses the bootloader. WinXP uses ACPI by default and implements its own hibernation method.)
Even with this version of GRUB, wmarcusm's programs will be still useful for re-enabling the feautures after waking up from suspend or APM hibernation.
One thing to note is that the port address is hardcoded. Smile Yes, it sounds stupid, but all three ThinPad 600E's that I have access to reports the same base i/o address for the south bridge. So far I had no problem on any of the three. If you do, probe it using wmarcusm's code and put that number in place of the existing hardcoded base address.
To use the feature, you just need to add "tpad" command to your boot configuration file. If you add the "--nods" option, it will only enable the l2 cache and leave the speedstep mod alone.
One final note is that, if you only have NTFS partitions, you cannot use this version of GRUB, as it lacks NTFS support. The stage2 images can be installed on linux or fat partitions. It will be great if it is ported to WINGRUB or GRUB4DOS. If you have no idea what I am talking about, just stay with your current configuration.
The source tar ball is available at: http://www-rtsl.cs.uiuc.edu/~klee7/grub-0.97tpad.tgz
512MB of RAM is supported
With the internal 32MB of PC-66 RAM disabled per the above CMOS edit, 2x256MB PC-100 SO-DIMMs (low density / 16 chips) are fully recognized and supported by the BIOS.