https://www.thinkwiki.org/w/index.php?title=SpeedStep&feed=atom&action=history
SpeedStep - Revision history
2024-03-29T05:27:28Z
Revision history for this page on the wiki
MediaWiki 1.31.12
https://www.thinkwiki.org/w/index.php?title=SpeedStep&diff=61213&oldid=prev
Bugmenot2: fixed london grammar
2020-11-15T17:58:13Z
<p>fixed london grammar</p>
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<td colspan="2" style="background-color: #fff; color: #222; text-align: center;">← Older revision</td>
<td colspan="2" style="background-color: #fff; color: #222; text-align: center;">Revision as of 17:58, 15 November 2020</td>
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<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|style="vertical-align:top;padding-right:20px;width:10px;white-space:nowrap;" | __TOC__</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|style="vertical-align:top;padding-right:20px;width:10px;white-space:nowrap;" | __TOC__</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|style="vertical-align:top" |</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|style="vertical-align:top" |</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>On January 18th, 2000, Intel released its Mobile Pentium 3 600 MHz CPU with <del class="diffchange diffchange-inline">its </del>proprietary [[Power Management|power management]] technology called SpeedStep.</div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>On January 18th, 2000, Intel released its Mobile Pentium 3 600 MHz CPU with <ins class="diffchange diffchange-inline">a </ins>proprietary [[Power Management|power management]] technology called SpeedStep<ins class="diffchange diffchange-inline">. This technology basically provides additional power saving modes for Intel's CPUs, it does not provide any sort of performance improvement</ins>.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del class="diffchange diffchange-inline">This technology provides additional power saving modes for Intel's CPUs to massively cut down on power consumption. Not </del>every revision of <del class="diffchange diffchange-inline">Intel's </del>SpeedStep are similar, therefore this page will attempt to document the <del class="diffchange diffchange-inline">changes and </del>behavior of every known SpeedStep revision.</div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins class="diffchange diffchange-inline">Please note that </ins>every revision of SpeedStep are similar <ins class="diffchange diffchange-inline">and may be confusing</ins>, therefore this page will attempt to document the behavior of every known SpeedStep revision.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|}</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|}</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>==Released==</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>==Released==</div></td></tr>
<tr><td colspan="2" class="diff-lineno" id="mw-diff-left-l11" >Line 11:</td>
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<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>Under AC power (in a charging or non-charging state), SpeedStep will automatically step into 'Maximum Performance Mode'. If the AC adapter is disconnected from the system, SpeedStep will automatically step into 'Battery Optimized Mode'. This behavior can be modified to some extent via issuing an instruction to either step into 'Maximum Performance Mode' without AC power, or step into 'Battery Optimized Mode' with AC power.</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>Under AC power (in a charging or non-charging state), SpeedStep will automatically step into 'Maximum Performance Mode'. If the AC adapter is disconnected from the system, SpeedStep will automatically step into 'Battery Optimized Mode'. This behavior can be modified to some extent via issuing an instruction to either step into 'Maximum Performance Mode' without AC power, or step into 'Battery Optimized Mode' with AC power.</div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;"></ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">The 'Coppermine' Mobile Pentium 3 used this revision of SpeedStep. No other Intel CPU has used this revision of SpeedStep.</ins></div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>===Enhanced Intel SpeedStep Technology (Geyserville-2)===</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>===Enhanced Intel SpeedStep Technology (Geyserville-2)===</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>This was a minor revision of the first SpeedStep that added a new feature called 'Demand-Based Switching <del class="diffchange diffchange-inline">(DBS)</del>'. The DBS alters the CPU's current power mode state via monitoring the CPU's load<del class="diffchange diffchange-inline">/usage</del>, by making it operate in 'Maximum Performance Mode' under high <del class="diffchange diffchange-inline">or </del>normal usage, and in 'Battery Optimized Mode' under low <del class="diffchange diffchange-inline">or </del>no usage.</div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>This was a minor revision of the first SpeedStep that added a new feature called 'Demand-Based Switching'. The DBS <ins class="diffchange diffchange-inline">function </ins>alters the CPU's current power mode state via monitoring the CPU's load, by making it operate in 'Maximum Performance Mode' under high <ins class="diffchange diffchange-inline">to </ins>normal usage, and in 'Battery Optimized Mode' under low <ins class="diffchange diffchange-inline">to </ins>no usage.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>There were no major changes made to SpeedStep's behavior, other than the fact that the transition between the two basic power modes were now controlled by the DBS feature. However, SpeedStep could still be issued an instruction to always stay in 'Maximum Performance Mode' or 'Battery Optimized Mode'.</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>There were no major changes made to SpeedStep's behavior, other than the fact that the transition between the two basic power modes were now controlled by the DBS feature. However, SpeedStep could still be issued an instruction to always stay in 'Maximum Performance Mode' or 'Battery Optimized Mode'.</div></td></tr>
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<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>This was a major revision of SpeedStep, which removed the overly simple 'two power modes with hard-wired predefined values' concept. It now has the ability to operate on a wide range of frequencies by switching the CPU's clock multiplier (by 1x steps, not 0.5x steps), which was not the case for the two previous revisions of SpeedStep. Additionally, it has the capability of controlling the CPU's core voltage with more precision (by 16 mV steps, or lesser depending on the CPU model), unlike the previous revisions which used only two core voltages.</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>This was a major revision of SpeedStep, which removed the overly simple 'two power modes with hard-wired predefined values' concept. It now has the ability to operate on a wide range of frequencies by switching the CPU's clock multiplier (by 1x steps, not 0.5x steps), which was not the case for the two previous revisions of SpeedStep. Additionally, it has the capability of controlling the CPU's core voltage with more precision (by 16 mV steps, or lesser depending on the CPU model), unlike the previous revisions which used only two core voltages.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>As SpeedStep was re-worked to take advantage of the aforementioned features, the behavior was also re-worked as well. In addition to the capability of controlling core voltage and clock frequencies via DBS, it is also capable of shutting down parts of the CPU to reduce power consumption, such as the L2 cache. In certain cases, the DBS feature (only from this revision of SpeedStep) is also known to utilize clock-gating to further reduce power consumption.</div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>As SpeedStep was re-worked to take advantage of the aforementioned features, the behavior was also re-worked as well. In addition to the capability of controlling core voltage and clock frequencies via DBS, it is also capable of shutting down parts of the CPU to reduce power consumption, such as the L2 cache. In certain cases, the DBS feature (only from this revision of SpeedStep) is also known to <ins class="diffchange diffchange-inline">heavily </ins>utilize clock-gating to further reduce power consumption.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>Due to the massive changes done to SpeedStep's behavior, only some features remain controllable by user intervention (such as core voltage adjustment, and clock frequency adjustment). The features that are not controllable, are clock-gating, and the automatic shutdown of the CPU's internal components.</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>Due to the massive changes done to SpeedStep's behavior, only some features remain controllable by user intervention (such as core voltage adjustment, and clock frequency adjustment). The features that are not controllable, are clock-gating, and the automatic shutdown of the CPU's internal components.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>The 'Banias' Pentium M<del class="diffchange diffchange-inline">, 'Dothan' Pentium M, </del>and the 'Prescott' Mobile Pentium 4, were the first to use this revision of SpeedStep. Newer Intel CPUs continue to utilize this revision of SpeedStep as well, although it was superseded by SpeedShift from Skylake <del class="diffchange diffchange-inline">and onwards</del>.</div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>The 'Banias' Pentium M and the 'Prescott' Mobile Pentium 4, were the first to use this revision of SpeedStep. Newer Intel CPUs continue to utilize this revision of SpeedStep as well, although it was superseded by SpeedShift <ins class="diffchange diffchange-inline">in newer Intel CPUs starting </ins>from Skylake.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>==Unreleased==</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>==Unreleased==</div></td></tr>
</table>
Bugmenot2
https://www.thinkwiki.org/w/index.php?title=SpeedStep&diff=60261&oldid=prev
Bugmenot2: added link to turbo boost page
2020-06-20T15:30:00Z
<p>added link to turbo boost page</p>
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<td colspan="2" style="background-color: #fff; color: #222; text-align: center;">← Older revision</td>
<td colspan="2" style="background-color: #fff; color: #222; text-align: center;">Revision as of 15:30, 20 June 2020</td>
</tr><tr><td colspan="2" class="diff-lineno" id="mw-diff-left-l32" >Line 32:</td>
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<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>Based off Geyserville-3, this was allegedly the enterprise variant of SpeedStep. It was originally supposed to be released in the form of 'Montecito' Itanium 2 CPUs, but it never materialized in the aforementioned CPUs. Only a concept exists for this particular revision of SpeedStep.</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>Based off Geyserville-3, this was allegedly the enterprise variant of SpeedStep. It was originally supposed to be released in the form of 'Montecito' Itanium 2 CPUs, but it never materialized in the aforementioned CPUs. Only a concept exists for this particular revision of SpeedStep.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>Unlike Geyserville's aim to reduce power consumption for every possible situation, Foxton's aim is to maximize power consumption for every possible situation, while additionally staying in a designated thermal design point. For example (TDP is defined as 130 watts in this example), an application that uses very little computing power of a Foxton-enabled CPU may draw only 50 watts at maximum load. The Foxton-enabled CPU, in reaction to this, would step up the core voltage and clock frequency to maximize the given TDP of 130 watts. This operating principle is similar to Intel's newer Turbo Boost technology, but with the additional capability of varying that maximization by 64 frequency steps and 32 voltage steps (the concept defines each voltage step as 12.5 mV each, frequency is unknown).</div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>Unlike Geyserville's aim to reduce power consumption for every possible situation, Foxton's aim is to maximize power consumption for every possible situation, while additionally staying in a designated thermal design point. For example (TDP is defined as 130 watts in this example), an application that uses very little computing power of a Foxton-enabled CPU may draw only 50 watts at maximum load. The Foxton-enabled CPU, in reaction to this, would step up the core voltage and clock frequency to maximize the given TDP of 130 watts. This operating principle is similar to Intel's newer <ins class="diffchange diffchange-inline">[[Turbo Boost|</ins>Turbo Boost technology<ins class="diffchange diffchange-inline">]]</ins>, but with the additional capability of varying that maximization by 64 frequency steps and 32 voltage steps (the concept defines each voltage step as 12.5 mV each, frequency is unknown).</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>Due to Foxton's complexity, it has its own controller (dubbed as the 'Foxton Controller') to manage these features. The Foxton Controller is also known to run at half of the CPU's maximum clock frequency, for an unknown reason. Not much else is known about Foxton.</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>Due to Foxton's complexity, it has its own controller (dubbed as the 'Foxton Controller') to manage these features. The Foxton Controller is also known to run at half of the CPU's maximum clock frequency, for an unknown reason. Not much else is known about Foxton.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>[[Category:Glossary]]</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>[[Category:Glossary]]</div></td></tr>
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Bugmenot2
https://www.thinkwiki.org/w/index.php?title=SpeedStep&diff=60257&oldid=prev
Bugmenot2: fixed london grammar
2020-06-20T09:21:31Z
<p>fixed london grammar</p>
<table class="diff diff-contentalign-left" data-mw="interface">
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<td colspan="2" style="background-color: #fff; color: #222; text-align: center;">← Older revision</td>
<td colspan="2" style="background-color: #fff; color: #222; text-align: center;">Revision as of 09:21, 20 June 2020</td>
</tr><tr><td colspan="2" class="diff-lineno" id="mw-diff-left-l13" >Line 13:</td>
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<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>===Enhanced Intel SpeedStep Technology (Geyserville-2)===</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>===Enhanced Intel SpeedStep Technology (Geyserville-2)===</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>This was a minor revision of the first SpeedStep that added a new feature called 'Demand-Based <del class="diffchange diffchange-inline">Processor Performance State Control </del>(DBS)'. The DBS alters the CPU's current power mode state via monitoring the CPU's load/usage, by making it operate in 'Maximum Performance Mode' under high or normal usage, and in 'Battery Optimized Mode' under low or no usage.</div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>This was a minor revision of the first SpeedStep that added a new feature called 'Demand-Based <ins class="diffchange diffchange-inline">Switching </ins>(DBS)'. The DBS alters the CPU's current power mode state via monitoring the CPU's load/usage, by making it operate in 'Maximum Performance Mode' under high or normal usage, and in 'Battery Optimized Mode' under low or no usage.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>There were no major changes made to SpeedStep's behavior, other than the fact that the transition between the two basic power modes were now controlled by the DBS feature. However, SpeedStep could still be issued an instruction to always stay in 'Maximum Performance Mode' or 'Battery Optimized Mode'.</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>There were no major changes made to SpeedStep's behavior, other than the fact that the transition between the two basic power modes were now controlled by the DBS feature. However, SpeedStep could still be issued an instruction to always stay in 'Maximum Performance Mode' or 'Battery Optimized Mode'.</div></td></tr>
<tr><td colspan="2" class="diff-lineno" id="mw-diff-left-l34" >Line 34:</td>
<td colspan="2" class="diff-lineno">Line 34:</td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>Unlike Geyserville's aim to reduce power consumption for every possible situation, Foxton's aim is to maximize power consumption for every possible situation, while additionally staying in a designated thermal design point. For example (TDP is defined as 130 watts in this example), an application that uses very little computing power of a Foxton-enabled CPU may draw only 50 watts at maximum load. The Foxton-enabled CPU, in reaction to this, would step up the core voltage and clock frequency to maximize the given TDP of 130 watts. This operating principle is similar to Intel's newer Turbo Boost technology, but with the additional capability of varying that maximization by 64 frequency steps and 32 voltage steps (the concept defines each voltage step as 12.5 mV each, frequency is unknown).</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>Unlike Geyserville's aim to reduce power consumption for every possible situation, Foxton's aim is to maximize power consumption for every possible situation, while additionally staying in a designated thermal design point. For example (TDP is defined as 130 watts in this example), an application that uses very little computing power of a Foxton-enabled CPU may draw only 50 watts at maximum load. The Foxton-enabled CPU, in reaction to this, would step up the core voltage and clock frequency to maximize the given TDP of 130 watts. This operating principle is similar to Intel's newer Turbo Boost technology, but with the additional capability of varying that maximization by 64 frequency steps and 32 voltage steps (the concept defines each voltage step as 12.5 mV each, frequency is unknown).</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>Due to Foxton's complexity, it has its own controller (dubbed as the 'Foxton Controller') to manage these features. The Foxton Controller is also known to run at half of the CPU's maximum clock frequency.</div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>Due to Foxton's complexity, it has its own controller (dubbed as the 'Foxton Controller') to manage these features. The Foxton Controller is also known to run at half of the CPU's maximum clock frequency<ins class="diffchange diffchange-inline">, for an unknown reason. Not much else is known about Foxton</ins>.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>[[Category:Glossary]]</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>[[Category:Glossary]]</div></td></tr>
</table>
Bugmenot2
https://www.thinkwiki.org/w/index.php?title=SpeedStep&diff=60256&oldid=prev
Bugmenot2: added more info
2020-06-19T13:51:49Z
<p>added more info</p>
<table class="diff diff-contentalign-left" data-mw="interface">
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<td colspan="2" style="background-color: #fff; color: #222; text-align: center;">Revision as of 13:51, 19 June 2020</td>
</tr><tr><td colspan="2" class="diff-lineno" id="mw-diff-left-l2" >Line 2:</td>
<td colspan="2" class="diff-lineno">Line 2:</td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|style="vertical-align:top;padding-right:20px;width:10px;white-space:nowrap;" | __TOC__</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|style="vertical-align:top;padding-right:20px;width:10px;white-space:nowrap;" | __TOC__</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|style="vertical-align:top" |</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|style="vertical-align:top" |</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>On January, <del class="diffchange diffchange-inline">18th </del>2000 Intel <del class="diffchange diffchange-inline">introduced the 600MHz [[Intel </del>Mobile Pentium <del class="diffchange diffchange-inline">III|Mobile Pentium III]] processor and </del>with <del class="diffchange diffchange-inline">it </del>its <del class="diffchange diffchange-inline">new </del>[[Power Management]] technology called SpeedStep.</div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>On January <ins class="diffchange diffchange-inline">18th</ins>, 2000<ins class="diffchange diffchange-inline">, </ins>Intel <ins class="diffchange diffchange-inline">released its </ins>Mobile Pentium <ins class="diffchange diffchange-inline">3 600 MHz CPU </ins>with its <ins class="diffchange diffchange-inline">proprietary </ins>[[Power Management<ins class="diffchange diffchange-inline">|power management</ins>]] technology called SpeedStep.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>This technology provides power saving modes for <del class="diffchange diffchange-inline">the CPU which consist of lowered CPU frequency and lowered CPU core voltage, so that overall </del>power consumption of the <del class="diffchange diffchange-inline">processor is reduced </del>and <del class="diffchange diffchange-inline">hence battery life extended</del>.</div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>This technology provides <ins class="diffchange diffchange-inline">additional </ins>power saving modes for <ins class="diffchange diffchange-inline">Intel's CPUs to massively cut down on </ins>power consumption<ins class="diffchange diffchange-inline">. Not every revision </ins>of <ins class="diffchange diffchange-inline">Intel's SpeedStep are similar, therefore this page will attempt to document </ins>the <ins class="diffchange diffchange-inline">changes </ins>and <ins class="diffchange diffchange-inline">behavior of every known SpeedStep revision</ins>.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|}</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|}</div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">==Released==</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">===Intel SpeedStep Technology (Geyserville)===</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">First introduced in the 'Coppermine' Mobile Pentium 3 CPUs ranging from 600-1000 MHz, it was extremely primitive in comparison to Transmeta's LongRun and AMD's PowerNow technologies. This is due to its bare-bones simplicity that consists of two power modes: 'Maximum Performance Mode' and 'Battery Optimized Mode'. Note that the two power modes had predefined core voltage and clock frequencies that could not be changed by software, as these were hard-wired during factory production.</ins></div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del class="diffchange diffchange-inline">==SpeedStep </del>(SpeedStep <del class="diffchange diffchange-inline">V1</del>.<del class="diffchange diffchange-inline">1)==</del></div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins class="diffchange diffchange-inline">Under AC power </ins>(<ins class="diffchange diffchange-inline">in a charging or non-charging state), </ins>SpeedStep <ins class="diffchange diffchange-inline">will automatically step into 'Maximum Performance Mode'</ins>. <ins class="diffchange diffchange-inline">If </ins>the <ins class="diffchange diffchange-inline">AC adapter is disconnected </ins>from <ins class="diffchange diffchange-inline">the system</ins>, SpeedStep <ins class="diffchange diffchange-inline">will automatically step into 'Battery Optimized Mode'</ins>. <ins class="diffchange diffchange-inline">This behavior can be modified to some extent via issuing an instruction to either step into 'Maximum Performance Mode' without </ins>AC power, <ins class="diffchange diffchange-inline">or step </ins>into <ins class="diffchange diffchange-inline">'Battery Optimized Mode' with AC </ins>power.</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del class="diffchange diffchange-inline">The original SpeedStep technology, featured in </del>the <del class="diffchange diffchange-inline">second generation [[Intel Mobile Pentium III|Mobile Pentium III]] processors </del>from <del class="diffchange diffchange-inline">600 to 1000 MHz, was rather primitive</del>, <del class="diffchange diffchange-inline">compared to recent standards. Processors featuring </del>SpeedStep <del class="diffchange diffchange-inline">are capable of running in two modes, the full power mode and the power save mode</del>. <del class="diffchange diffchange-inline">As soon as </del>AC power <del class="diffchange diffchange-inline">is removed</del>, <del class="diffchange diffchange-inline">the processor switches </del>into <del class="diffchange diffchange-inline">powersave mode and remains there, independent of the systems CPU load. It is, however, possible for the user to switch it back to full </del>power <del class="diffchange diffchange-inline">mode manually</del>.</div></td><td colspan="2"> </td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>==Enhanced SpeedStep (<del class="diffchange diffchange-inline">SpeedStep V2.1</del>)==</div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins class="diffchange diffchange-inline">=</ins>==Enhanced <ins class="diffchange diffchange-inline">Intel </ins>SpeedStep <ins class="diffchange diffchange-inline">Technology </ins>(<ins class="diffchange diffchange-inline">Geyserville-2</ins>)<ins class="diffchange diffchange-inline">=</ins>==</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del class="diffchange diffchange-inline">Introduced with </del>the <del class="diffchange diffchange-inline">[[Intel Mobile Pentium III</del>-<del class="diffchange diffchange-inline">M|Mobile Pentium III-M]] processors, Enhanced Speedstep added </del>the <del class="diffchange diffchange-inline">capability to automatically switch between </del>the <del class="diffchange diffchange-inline">two frequencies based on current </del>CPU load<del class="diffchange diffchange-inline">. Hence these CPUs can </del>operate in <del class="diffchange diffchange-inline">three modes: the powersave mode</del>, <del class="diffchange diffchange-inline">the performance mode </del>and <del class="diffchange diffchange-inline">the automatic mode. Intel calls this enhancement Demand Based Switching</del>.</div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins class="diffchange diffchange-inline">This was a minor revision of </ins>the <ins class="diffchange diffchange-inline">first SpeedStep that added a new feature called 'Demand</ins>-<ins class="diffchange diffchange-inline">Based Processor Performance State Control (DBS)'. The DBS alters </ins>the <ins class="diffchange diffchange-inline">CPU's current power mode state via monitoring </ins>the CPU<ins class="diffchange diffchange-inline">'s </ins>load<ins class="diffchange diffchange-inline">/usage, by making it </ins>operate in <ins class="diffchange diffchange-inline">'Maximum Performance Mode' under high or normal usage</ins>, and <ins class="diffchange diffchange-inline">in 'Battery Optimized Mode' under low or no usage</ins>.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del class="diffchange diffchange-inline">==Enhanced SpeedStep (SpeedStep V2.2)==</del></div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins class="diffchange diffchange-inline">There were no major changes made to </ins>SpeedStep<ins class="diffchange diffchange-inline">'s behavior</ins>, <ins class="diffchange diffchange-inline">other than </ins>the <ins class="diffchange diffchange-inline">fact that the transition between the two basic power modes were now controlled by the DBS feature</ins>. <ins class="diffchange diffchange-inline">However, SpeedStep could still be issued an instruction </ins>to <ins class="diffchange diffchange-inline">always stay in 'Maximum Performance Mode' or 'Battery Optimized Mode'</ins>.</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del class="diffchange diffchange-inline">The </del>SpeedStep <del class="diffchange diffchange-inline">technology integrated into [[Intel Mobile Pentium 4-M|Mobile Pentium 4-M]] processors has another feature</del>, <del class="diffchange diffchange-inline">called </del>the <del class="diffchange diffchange-inline">Deep Alert mode</del>. <del class="diffchange diffchange-inline">Intel states this mode enables the processor </del>to <del class="diffchange diffchange-inline">run at even lower voltage levels, thus saving even more battery life</del>.</div></td><td colspan="2"> </td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del class="diffchange diffchange-inline">==EIST (SpeedStep </del>3<del class="diffchange diffchange-inline">)==</del></div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins class="diffchange diffchange-inline">The 'Tualatin' Mobile Pentium </ins>3<ins class="diffchange diffchange-inline">-M</ins>, <ins class="diffchange diffchange-inline">'Northwood' Mobile </ins>Pentium <ins class="diffchange diffchange-inline">4-</ins>M, <ins class="diffchange diffchange-inline">and the 'Northwood' Mobile Pentium </ins>4, <ins class="diffchange diffchange-inline">used this particular revision of SpeedStep for their power management capabilities</ins>.</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del class="diffchange diffchange-inline">Because changing names is cool, the third generation of the processor power management feature is called EIST. The major improvement is that these processors are not only able to switch between two frequencies (high and low), but can dynamically change over a range of frequencies</del>, <del class="diffchange diffchange-inline">usually in steps of 100 MHz. I.e. a </del>Pentium M <del class="diffchange diffchange-inline">with 1.5 GHz can run at frequencies of 1.5</del>, <del class="diffchange diffchange-inline">1.</del>4, <del class="diffchange diffchange-inline">1.3, 1.2, 1.1, 1.0, 0.9, 0.8, 0.7 and 0.6 GHz</del>.</div></td><td colspan="2"> </td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>==(<del class="diffchange diffchange-inline">Enhanced</del>) <del class="diffchange diffchange-inline">EIST</del>==</div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>==<ins class="diffchange diffchange-inline">=Enhanced Intel SpeedStep Technology </ins>(<ins class="diffchange diffchange-inline">Geyserville-3</ins>)<ins class="diffchange diffchange-inline">=</ins>==</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del class="diffchange diffchange-inline">The EIST featured in [[Intel Pentium M </del>(<del class="diffchange diffchange-inline">Banias</del>)<del class="diffchange diffchange-inline">|Pentium M]] is furthermore able to switch off momentarily unneeded parts </del>of the <del class="diffchange diffchange-inline">processor</del>'s <del class="diffchange diffchange-inline">usually very power consuming L2-Cache</del>.</div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins class="diffchange diffchange-inline">This was a major revision of SpeedStep, which removed the overly simple 'two power modes with hard-wired predefined values' concept. It now has the ability to operate on a wide range of frequencies by switching the CPU's clock multiplier </ins>(<ins class="diffchange diffchange-inline">by 1x steps, not 0.5x steps</ins>)<ins class="diffchange diffchange-inline">, which was not the case for the two previous revisions of SpeedStep. Additionally, it has the capability </ins>of <ins class="diffchange diffchange-inline">controlling </ins>the <ins class="diffchange diffchange-inline">CPU</ins>'s <ins class="diffchange diffchange-inline">core voltage with more precision (by 16 mV steps, or lesser depending on the CPU model), unlike the previous revisions which used only two core voltages</ins>.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">As SpeedStep was re-worked to take advantage of the aforementioned features, the behavior was also re-worked as well. In addition to the capability of controlling core voltage and clock frequencies via DBS, it is also capable of shutting down parts of the CPU to reduce power consumption, such as the L2 cache. In certain cases, the DBS feature (only from this revision of SpeedStep) is also known to utilize clock-gating to further reduce power consumption.</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;"></ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">Due to the massive changes done to SpeedStep's behavior, only some features remain controllable by user intervention (such as core voltage adjustment, and clock frequency adjustment). The features that are not controllable, are clock-gating, and the automatic shutdown of the CPU's internal components.</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;"></ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">The 'Banias' Pentium M, 'Dothan' Pentium M, and the 'Prescott' Mobile Pentium 4, were the first to use this revision of SpeedStep. Newer Intel CPUs continue to utilize this revision of SpeedStep as well, although it was superseded by SpeedShift from Skylake and onwards.</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;"></ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">==Unreleased==</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">===Enhanced Intel SpeedStep Technology (Foxton)===</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">Based off Geyserville-3, this was allegedly the enterprise variant of SpeedStep. It was originally supposed to be released in the form of 'Montecito' Itanium 2 CPUs, but it never materialized in the aforementioned CPUs. Only a concept exists for this particular revision of SpeedStep.</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;"></ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">Unlike Geyserville's aim to reduce power consumption for every possible situation, Foxton's aim is to maximize power consumption for every possible situation, while additionally staying in a designated thermal design point. For example (TDP is defined as 130 watts in this example), an application that uses very little computing power of a Foxton-enabled CPU may draw only 50 watts at maximum load. The Foxton-enabled CPU, in reaction to this, would step up the core voltage and clock frequency to maximize the given TDP of 130 watts. This operating principle is similar to Intel's newer Turbo Boost technology, but with the additional capability of varying that maximization by 64 frequency steps and 32 voltage steps (the concept defines each voltage step as 12.5 mV each, frequency is unknown).</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;"></ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">Due to Foxton's complexity, it has its own controller (dubbed as the 'Foxton Controller') to manage these features. The Foxton Controller is also known to run at half of the CPU's maximum clock frequency.</ins></div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>[[Category:Glossary]]</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>[[Category:Glossary]]</div></td></tr>
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Bugmenot2
https://www.thinkwiki.org/w/index.php?title=SpeedStep&diff=16893&oldid=prev
Whizkid: Minor grammar and spelling
2005-10-03T13:40:58Z
<p>Minor grammar and spelling</p>
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<td colspan="2" style="background-color: #fff; color: #222; text-align: center;">Revision as of 13:40, 3 October 2005</td>
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<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|style="vertical-align:top;padding-right:20px;width:10px;white-space:nowrap;" | __TOC__</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|style="vertical-align:top;padding-right:20px;width:10px;white-space:nowrap;" | __TOC__</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|style="vertical-align:top" |</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|style="vertical-align:top" |</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>On January, 18th 2000 Intel introduced the 600MHz [[Intel Mobile Pentium III|Mobile Pentium III]] processor and with it <del class="diffchange diffchange-inline">it's </del>new [[Power Management]] technology called SpeedStep.</div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>On January, 18th 2000 Intel introduced the 600MHz [[Intel Mobile Pentium III|Mobile Pentium III]] processor and with it <ins class="diffchange diffchange-inline">its </ins>new [[Power Management]] technology called SpeedStep.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>This technology <del class="diffchange diffchange-inline">basically </del>provides <del class="diffchange diffchange-inline">powersave </del>modes for the CPU which consist of lowered CPU frequency and lowered CPU core voltage, so that overall power <del class="diffchange diffchange-inline">consumtion </del>of the processor is reduced and hence battery life extended.</div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>This technology provides <ins class="diffchange diffchange-inline">power saving </ins>modes for the CPU which consist of lowered CPU frequency and lowered CPU core voltage, so that overall power <ins class="diffchange diffchange-inline">consumption </ins>of the processor is reduced and hence battery life extended.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|}</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|}</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td colspan="2" class="diff-lineno" id="mw-diff-left-l20" >Line 20:</td>
<td colspan="2" class="diff-lineno">Line 20:</td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>==(Enhanced) EIST==</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>==(Enhanced) EIST==</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>The EIST featured in [[Intel Pentium M (Banias)|Pentium M]] is furthermore able to switch off momentarily unneeded parts of the <del class="diffchange diffchange-inline">processors </del>usually very power consuming L2-Cache.</div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>The EIST featured in [[Intel Pentium M (Banias)|Pentium M]] is furthermore able to switch off momentarily unneeded parts of the <ins class="diffchange diffchange-inline">processor's </ins>usually very power consuming L2-Cache.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>[[Category:Glossary]]</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>[[Category:Glossary]]</div></td></tr>
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Whizkid
https://www.thinkwiki.org/w/index.php?title=SpeedStep&diff=9611&oldid=prev
84.191.172.212 at 01:34, 6 August 2005
2005-08-06T01:34:27Z
<p></p>
<table class="diff diff-contentalign-left" data-mw="interface">
<col class="diff-marker" />
<col class="diff-content" />
<col class="diff-marker" />
<col class="diff-content" />
<tr class="diff-title" lang="en">
<td colspan="2" style="background-color: #fff; color: #222; text-align: center;">← Older revision</td>
<td colspan="2" style="background-color: #fff; color: #222; text-align: center;">Revision as of 01:34, 6 August 2005</td>
</tr><tr><td colspan="2" class="diff-lineno" id="mw-diff-left-l4" >Line 4:</td>
<td colspan="2" class="diff-lineno">Line 4:</td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>On January, 18th 2000 Intel introduced the 600MHz [[Intel Mobile Pentium III|Mobile Pentium III]] processor and with it it's new [[Power Management]] technology called SpeedStep.</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>On January, 18th 2000 Intel introduced the 600MHz [[Intel Mobile Pentium III|Mobile Pentium III]] processor and with it it's new [[Power Management]] technology called SpeedStep.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>This technology provides powersave modes for the CPU which consist of lowered CPU frequency and lowered CPU core voltage, so that overall power consumtion of the processor is reduced and hence battery life extended.</div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>This technology <ins class="diffchange diffchange-inline">basically </ins>provides powersave modes for the CPU which consist of lowered CPU frequency and lowered CPU core voltage, so that overall power consumtion of the processor is reduced and hence battery life extended.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|}</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|}</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
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84.191.172.212
https://www.thinkwiki.org/w/index.php?title=SpeedStep&diff=7299&oldid=prev
84.191.172.212 at 01:34, 6 August 2005
2005-08-06T01:34:04Z
<p></p>
<table class="diff diff-contentalign-left" data-mw="interface">
<col class="diff-marker" />
<col class="diff-content" />
<col class="diff-marker" />
<col class="diff-content" />
<tr class="diff-title" lang="en">
<td colspan="2" style="background-color: #fff; color: #222; text-align: center;">← Older revision</td>
<td colspan="2" style="background-color: #fff; color: #222; text-align: center;">Revision as of 01:34, 6 August 2005</td>
</tr><tr><td colspan="2" class="diff-lineno" id="mw-diff-left-l3" >Line 3:</td>
<td colspan="2" class="diff-lineno">Line 3:</td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|style="vertical-align:top" |</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|style="vertical-align:top" |</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>On January, 18th 2000 Intel introduced the 600MHz [[Intel Mobile Pentium III|Mobile Pentium III]] processor and with it it's new [[Power Management]] technology called SpeedStep.</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>On January, 18th 2000 Intel introduced the 600MHz [[Intel Mobile Pentium III|Mobile Pentium III]] processor and with it it's new [[Power Management]] technology called SpeedStep.</div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;"></ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">This technology provides powersave modes for the CPU which consist of lowered CPU frequency and lowered CPU core voltage, so that overall power consumtion of the processor is reduced and hence battery life extended.</ins></div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|}</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>|}</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
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84.191.172.212
https://www.thinkwiki.org/w/index.php?title=SpeedStep&diff=7298&oldid=prev
84.191.172.212 at 01:27, 6 August 2005
2005-08-06T01:27:42Z
<p></p>
<table class="diff diff-contentalign-left" data-mw="interface">
<col class="diff-marker" />
<col class="diff-content" />
<col class="diff-marker" />
<col class="diff-content" />
<tr class="diff-title" lang="en">
<td colspan="2" style="background-color: #fff; color: #222; text-align: center;">← Older revision</td>
<td colspan="2" style="background-color: #fff; color: #222; text-align: center;">Revision as of 01:27, 6 August 2005</td>
</tr><tr><td colspan="2" class="diff-lineno" id="mw-diff-left-l1" >Line 1:</td>
<td colspan="2" class="diff-lineno">Line 1:</td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">{| width="100%"</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">|style="vertical-align:top;padding-right:20px;width:10px;white-space:nowrap;" | __TOC__</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">|style="vertical-align:top" |</ins></div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>On January, 18th 2000 Intel introduced the 600MHz [[Intel Mobile Pentium III|Mobile Pentium III]] processor and with it it's new [[Power Management]] technology called SpeedStep.</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>On January, 18th 2000 Intel introduced the 600MHz [[Intel Mobile Pentium III|Mobile Pentium III]] processor and with it it's new [[Power Management]] technology called SpeedStep.</div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">|}</ins></div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>==SpeedStep (SpeedStep V1.1)==</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>==SpeedStep (SpeedStep V1.1)==</div></td></tr>
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</table>
84.191.172.212
https://www.thinkwiki.org/w/index.php?title=SpeedStep&diff=7296&oldid=prev
84.191.150.41: /* (Enhanced) EIST */
2005-08-06T00:02:18Z
<p><span dir="auto"><span class="autocomment">(Enhanced) EIST</span></span></p>
<table class="diff diff-contentalign-left" data-mw="interface">
<col class="diff-marker" />
<col class="diff-content" />
<col class="diff-marker" />
<col class="diff-content" />
<tr class="diff-title" lang="en">
<td colspan="2" style="background-color: #fff; color: #222; text-align: center;">← Older revision</td>
<td colspan="2" style="background-color: #fff; color: #222; text-align: center;">Revision as of 00:02, 6 August 2005</td>
</tr><tr><td colspan="2" class="diff-lineno" id="mw-diff-left-l14" >Line 14:</td>
<td colspan="2" class="diff-lineno">Line 14:</td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>==(Enhanced) EIST==</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>==(Enhanced) EIST==</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>The EIST featured in [[Intel Pentium M|Pentium M]] is furthermore able to switch off momentarily unneeded parts of the processors usually very power consuming L2-Cache.</div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>The EIST featured in [[Intel Pentium M <ins class="diffchange diffchange-inline">(Banias)</ins>|Pentium M]] is furthermore able to switch off momentarily unneeded parts of the processors usually very power consuming L2-Cache.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>[[Category:Glossary]]</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>[[Category:Glossary]]</div></td></tr>
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84.191.150.41
https://www.thinkwiki.org/w/index.php?title=SpeedStep&diff=7279&oldid=prev
84.191.150.41 at 00:01, 6 August 2005
2005-08-06T00:01:58Z
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<td colspan="2" style="background-color: #fff; color: #222; text-align: center;">← Older revision</td>
<td colspan="2" style="background-color: #fff; color: #222; text-align: center;">Revision as of 00:01, 6 August 2005</td>
</tr><tr><td colspan="2" class="diff-lineno" id="mw-diff-left-l1" >Line 1:</td>
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<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>On January, 18th 2000 Intel introduced the 600MHz [[Intel Mobile Pentium III|Mobile Pentium III]] processor and with it it's new Power Management technology called SpeedStep.</div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>On January, 18th 2000 Intel introduced the 600MHz [[Intel Mobile Pentium III|Mobile Pentium III]] processor and with it it's new <ins class="diffchange diffchange-inline">[[</ins>Power Management<ins class="diffchange diffchange-inline">]] </ins>technology called SpeedStep.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>==SpeedStep==</div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>==SpeedStep <ins class="diffchange diffchange-inline">(SpeedStep V1.1)</ins>==</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>The original SpeedStep technology, featured in the second generation Mobile Pentium III processors from 600 to 1000 MHz, was rather primitive. <del class="diffchange diffchange-inline">The processor was </del>capable of running in two modes, the full power mode and the power save mode. As soon as AC power <del class="diffchange diffchange-inline">was </del>removed, the processor <del class="diffchange diffchange-inline">switched </del>into <del class="diffchange diffchange-inline">power save </del>mode and <del class="diffchange diffchange-inline">remained </del>there, independent of the systems CPU load. It <del class="diffchange diffchange-inline">was</del>, however, possible for the user to switch it back to full power mode manually.  </div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>The original SpeedStep technology, featured in the second generation <ins class="diffchange diffchange-inline">[[Intel Mobile Pentium III|</ins>Mobile Pentium III<ins class="diffchange diffchange-inline">]] </ins>processors from 600 to 1000 MHz, was rather primitive<ins class="diffchange diffchange-inline">, compared to recent standards</ins>. <ins class="diffchange diffchange-inline">Processors featuring SpeedStep are </ins>capable of running in two modes, the full power mode and the power save mode. As soon as AC power <ins class="diffchange diffchange-inline">is </ins>removed, the processor <ins class="diffchange diffchange-inline">switches </ins>into <ins class="diffchange diffchange-inline">powersave </ins>mode and <ins class="diffchange diffchange-inline">remains </ins>there, independent of the systems CPU load. It <ins class="diffchange diffchange-inline">is</ins>, however, possible for the user to switch it back to full power mode manually.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>==Enhanced SpeedStep==</div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>==Enhanced SpeedStep <ins class="diffchange diffchange-inline">(SpeedStep V2.1)</ins>==</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del class="diffchange diffchange-inline">Indroduced </del>with the Mobile Pentium III-M processors, Enhanced Speedstep added the capability to automatically switch between the two frequencies based on current CPU load.</div></td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins class="diffchange diffchange-inline">Introduced </ins>with the <ins class="diffchange diffchange-inline">[[Intel </ins>Mobile Pentium III-M<ins class="diffchange diffchange-inline">|Mobile Pentium III-M]] </ins>processors, Enhanced Speedstep added the capability to automatically switch between the two frequencies based on current CPU load<ins class="diffchange diffchange-inline">. Hence these CPUs can operate in three modes: the powersave mode, the performance mode and the automatic mode. Intel calls this enhancement Demand Based Switching.</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div> </div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins class="diffchange diffchange-inline">==Enhanced SpeedStep (SpeedStep V2.2)==</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins class="diffchange diffchange-inline">The SpeedStep technology integrated into [[Intel Mobile Pentium 4-M|Mobile Pentium 4-M]] processors has another feature, called the Deep Alert mode. Intel states this mode enables the processor to run at even lower voltage levels, thus saving even more battery life.</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div> </div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins class="diffchange diffchange-inline">==EIST (SpeedStep 3)==</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins class="diffchange diffchange-inline">Because changing names is cool, the third generation of the processor power management feature is called EIST. The major improvement is that these processors are not only able to switch between two frequencies (high and low), but can dynamically change over a range of frequencies, usually in steps of 100 MHz. I.e. a Pentium M with 1.5 GHz can run at frequencies of 1.5, 1.4, 1.3, 1.2, 1.1, 1.0, 0.9, 0.8, 0.7 and 0.6 GHz.</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div> </div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins class="diffchange diffchange-inline">==(Enhanced) EIST==</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins class="diffchange diffchange-inline">The EIST featured in [[Intel Pentium M|Pentium M]] is furthermore able to switch off momentarily unneeded parts of the processors usually very power consuming L2-Cache</ins>.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #222; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
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84.191.150.41