Difference between revisions of "SpeedStep"

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On January, 18th 2000 Intel introduced the 600MHz [[Intel Mobile Pentium III|Mobile Pentium III]] processor and with it its new [[Power Management]] technology called SpeedStep.
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On January 18th, 2000, Intel released its Mobile Pentium 3 600 MHz CPU with its proprietary [[Power Management|power management]] technology called SpeedStep.
  
This technology provides power saving modes for the CPU which consist of lowered CPU frequency and lowered CPU core voltage, so that overall power consumption of the processor is reduced and hence battery life extended.
+
This technology provides additional power saving modes for Intel's CPUs to massively cut down on power consumption. Not every revision of Intel's SpeedStep are similar, therefore this page will attempt to document the changes and behavior of every known SpeedStep revision.
 
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==Released==
 +
===Intel SpeedStep Technology (Geyserville)===
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First introduced in the 'Coppermine' Mobile Pentium 3 CPUs ranging from 600-1000 MHz, it was extremely primitive in comparison to Transmeta's LongRun and AMD's PowerNow technologies. This is due to its bare-bones simplicity that consists of two power modes: 'Maximum Performance Mode' and 'Battery Optimized Mode'. Note that the two power modes had predefined core voltage and clock frequencies that could not be changed by software, as these were hard-wired during factory production.
  
==SpeedStep (SpeedStep V1.1)==
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Under AC power (in a charging or non-charging state), SpeedStep will automatically step into 'Maximum Performance Mode'. If the AC adapter is disconnected from the system, SpeedStep will automatically step into 'Battery Optimized Mode'. This behavior can be modified to some extent via issuing an instruction to either step into 'Maximum Performance Mode' without AC power, or step into 'Battery Optimized Mode' with AC power.
The original SpeedStep technology, featured in the second generation [[Intel Mobile Pentium III|Mobile Pentium III]] processors from 600 to 1000 MHz, was rather primitive, compared to recent standards. Processors featuring SpeedStep are capable of running in two modes, the full power mode and the power save mode. As soon as AC power is removed, the processor switches into powersave mode and remains there, independent of the systems CPU load. It is, however, possible for the user to switch it back to full power mode manually.
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==Enhanced SpeedStep (SpeedStep V2.1)==
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===Enhanced Intel SpeedStep Technology (Geyserville-2)===
Introduced with the [[Intel Mobile Pentium III-M|Mobile Pentium III-M]] processors, Enhanced Speedstep added the capability to automatically switch between the two frequencies based on current CPU load. Hence these CPUs can operate in three modes: the powersave mode, the performance mode and the automatic mode. Intel calls this enhancement Demand Based Switching.
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This was a minor revision of the first SpeedStep that added a new feature called 'Demand-Based Processor Performance State Control (DBS)'. The DBS alters the CPU's current power mode state via monitoring the CPU's load/usage, by making it operate in 'Maximum Performance Mode' under high or normal usage, and in 'Battery Optimized Mode' under low or no usage.
  
==Enhanced SpeedStep (SpeedStep V2.2)==
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There were no major changes made to SpeedStep's behavior, other than the fact that the transition between the two basic power modes were now controlled by the DBS feature. However, SpeedStep could still be issued an instruction to always stay in 'Maximum Performance Mode' or 'Battery Optimized Mode'.
The SpeedStep technology integrated into [[Intel Mobile Pentium 4-M|Mobile Pentium 4-M]] processors has another feature, called the Deep Alert mode. Intel states this mode enables the processor to run at even lower voltage levels, thus saving even more battery life.
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==EIST (SpeedStep 3)==
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The 'Tualatin' Mobile Pentium 3-M, 'Northwood' Mobile Pentium 4-M, and the 'Northwood' Mobile Pentium 4, used this particular revision of SpeedStep for their power management capabilities.
Because changing names is cool, the third generation of the processor power management feature is called EIST. The major improvement is that these processors are not only able to switch between two frequencies (high and low), but can dynamically change over a range of frequencies, usually in steps of 100 MHz. I.e. a Pentium M with 1.5 GHz can run at frequencies of 1.5, 1.4, 1.3, 1.2, 1.1, 1.0, 0.9, 0.8, 0.7 and 0.6 GHz.
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==(Enhanced) EIST==
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===Enhanced Intel SpeedStep Technology (Geyserville-3)===
The EIST featured in [[Intel Pentium M (Banias)|Pentium M]] is furthermore able to switch off momentarily unneeded parts of the processor's usually very power consuming L2-Cache.
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This was a major revision of SpeedStep, which removed the overly simple 'two power modes with hard-wired predefined values' concept. It now has the ability to operate on a wide range of frequencies by switching the CPU's clock multiplier (by 1x steps, not 0.5x steps), which was not the case for the two previous revisions of SpeedStep. Additionally, it has the capability of controlling the CPU's core voltage with more precision (by 16 mV steps, or lesser depending on the CPU model), unlike the previous revisions which used only two core voltages.
  
 +
As SpeedStep was re-worked to take advantage of the aforementioned features, the behavior was also re-worked as well. In addition to the capability of controlling core voltage and clock frequencies via DBS, it is also capable of shutting down parts of the CPU to reduce power consumption, such as the L2 cache. In certain cases, the DBS feature (only from this revision of SpeedStep) is also known to utilize clock-gating to further reduce power consumption.
 +
 +
Due to the massive changes done to SpeedStep's behavior, only some features remain controllable by user intervention (such as core voltage adjustment, and clock frequency adjustment). The features that are not controllable, are clock-gating, and the automatic shutdown of the CPU's internal components.
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 +
The 'Banias' Pentium M, 'Dothan' Pentium M, and the 'Prescott' Mobile Pentium 4, were the first to use this revision of SpeedStep. Newer Intel CPUs continue to utilize this revision of SpeedStep as well, although it was superseded by SpeedShift from Skylake and onwards.
 +
 +
==Unreleased==
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===Enhanced Intel SpeedStep Technology (Foxton)===
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Based off Geyserville-3, this was allegedly the enterprise variant of SpeedStep. It was originally supposed to be released in the form of 'Montecito' Itanium 2 CPUs, but it never materialized in the aforementioned CPUs. Only a concept exists for this particular revision of SpeedStep.
 +
 +
Unlike Geyserville's aim to reduce power consumption for every possible situation, Foxton's aim is to maximize power consumption for every possible situation, while additionally staying in a designated thermal design point. For example (TDP is defined as 130 watts in this example), an application that uses very little computing power of a Foxton-enabled CPU may draw only 50 watts at maximum load. The Foxton-enabled CPU, in reaction to this, would step up the core voltage and clock frequency to maximize the given TDP of 130 watts. This operating principle is similar to Intel's newer Turbo Boost technology, but with the additional capability of varying that maximization by 64 frequency steps and 32 voltage steps (the concept defines each voltage step as 12.5 mV each, frequency is unknown).
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Due to Foxton's complexity, it has its own controller (dubbed as the 'Foxton Controller') to manage these features. The Foxton Controller is also known to run at half of the CPU's maximum clock frequency.
  
 
[[Category:Glossary]]
 
[[Category:Glossary]]

Revision as of 15:51, 19 June 2020

On January 18th, 2000, Intel released its Mobile Pentium 3 600 MHz CPU with its proprietary power management technology called SpeedStep.

This technology provides additional power saving modes for Intel's CPUs to massively cut down on power consumption. Not every revision of Intel's SpeedStep are similar, therefore this page will attempt to document the changes and behavior of every known SpeedStep revision.

Released

Intel SpeedStep Technology (Geyserville)

First introduced in the 'Coppermine' Mobile Pentium 3 CPUs ranging from 600-1000 MHz, it was extremely primitive in comparison to Transmeta's LongRun and AMD's PowerNow technologies. This is due to its bare-bones simplicity that consists of two power modes: 'Maximum Performance Mode' and 'Battery Optimized Mode'. Note that the two power modes had predefined core voltage and clock frequencies that could not be changed by software, as these were hard-wired during factory production.

Under AC power (in a charging or non-charging state), SpeedStep will automatically step into 'Maximum Performance Mode'. If the AC adapter is disconnected from the system, SpeedStep will automatically step into 'Battery Optimized Mode'. This behavior can be modified to some extent via issuing an instruction to either step into 'Maximum Performance Mode' without AC power, or step into 'Battery Optimized Mode' with AC power.

Enhanced Intel SpeedStep Technology (Geyserville-2)

This was a minor revision of the first SpeedStep that added a new feature called 'Demand-Based Processor Performance State Control (DBS)'. The DBS alters the CPU's current power mode state via monitoring the CPU's load/usage, by making it operate in 'Maximum Performance Mode' under high or normal usage, and in 'Battery Optimized Mode' under low or no usage.

There were no major changes made to SpeedStep's behavior, other than the fact that the transition between the two basic power modes were now controlled by the DBS feature. However, SpeedStep could still be issued an instruction to always stay in 'Maximum Performance Mode' or 'Battery Optimized Mode'.

The 'Tualatin' Mobile Pentium 3-M, 'Northwood' Mobile Pentium 4-M, and the 'Northwood' Mobile Pentium 4, used this particular revision of SpeedStep for their power management capabilities.

Enhanced Intel SpeedStep Technology (Geyserville-3)

This was a major revision of SpeedStep, which removed the overly simple 'two power modes with hard-wired predefined values' concept. It now has the ability to operate on a wide range of frequencies by switching the CPU's clock multiplier (by 1x steps, not 0.5x steps), which was not the case for the two previous revisions of SpeedStep. Additionally, it has the capability of controlling the CPU's core voltage with more precision (by 16 mV steps, or lesser depending on the CPU model), unlike the previous revisions which used only two core voltages.

As SpeedStep was re-worked to take advantage of the aforementioned features, the behavior was also re-worked as well. In addition to the capability of controlling core voltage and clock frequencies via DBS, it is also capable of shutting down parts of the CPU to reduce power consumption, such as the L2 cache. In certain cases, the DBS feature (only from this revision of SpeedStep) is also known to utilize clock-gating to further reduce power consumption.

Due to the massive changes done to SpeedStep's behavior, only some features remain controllable by user intervention (such as core voltage adjustment, and clock frequency adjustment). The features that are not controllable, are clock-gating, and the automatic shutdown of the CPU's internal components.

The 'Banias' Pentium M, 'Dothan' Pentium M, and the 'Prescott' Mobile Pentium 4, were the first to use this revision of SpeedStep. Newer Intel CPUs continue to utilize this revision of SpeedStep as well, although it was superseded by SpeedShift from Skylake and onwards.

Unreleased

Enhanced Intel SpeedStep Technology (Foxton)

Based off Geyserville-3, this was allegedly the enterprise variant of SpeedStep. It was originally supposed to be released in the form of 'Montecito' Itanium 2 CPUs, but it never materialized in the aforementioned CPUs. Only a concept exists for this particular revision of SpeedStep.

Unlike Geyserville's aim to reduce power consumption for every possible situation, Foxton's aim is to maximize power consumption for every possible situation, while additionally staying in a designated thermal design point. For example (TDP is defined as 130 watts in this example), an application that uses very little computing power of a Foxton-enabled CPU may draw only 50 watts at maximum load. The Foxton-enabled CPU, in reaction to this, would step up the core voltage and clock frequency to maximize the given TDP of 130 watts. This operating principle is similar to Intel's newer Turbo Boost technology, but with the additional capability of varying that maximization by 64 frequency steps and 32 voltage steps (the concept defines each voltage step as 12.5 mV each, frequency is unknown).

Due to Foxton's complexity, it has its own controller (dubbed as the 'Foxton Controller') to manage these features. The Foxton Controller is also known to run at half of the CPU's maximum clock frequency.